How can I know if e10_avl_st_gen.v and e10_avl_st_mon.v in filelist.txt be included in compilation of original vendor design example eth_e2e_e10?

Hi,

You need to include it and it cannot be removed. It is used in the design

Hi JohnT,

May I know more detail about that ?what that 2 files for ?

and what is the diffrentce comparing to below 2 files

/root/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/eth_e2e_e10/hw/rtl/e10/eth_traffic_controller/avalon_st_gen.v

/root/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/eth_e2e_e10/hw/rtl/e10/eth_traffic_controller/avalon_st_mon.v

thanks

jim

Hi,

Avalon_st_gen.v is the Avalon ST Generator and Avalon_st_mon.v is the monitor IP. It is a IP used to performed traffic validation on your system.

The e10_avl_st_gen.v and e10_avl_st_mon.v is the high level design which will call the the Avalon_st_gen.v and avalon_st_mon.v file in order to incorporate the Ethernet validation using the Avalon ST packet.

Hi JotnT,

Thanks for your feedback.

May I know where can I find this parent-child relationship between these similar but diffrent module?

I have fond the parent module of Avalon_st_gen.v and eth_std_traffic_controller_top, is eth_std_traffic_controller_top from the synthesis view under ccip_std_afu/prz0/lp0.[0].eth[0]/gen_mon_inst/

I have not found the top module of avalon_st_gen being installed in e10_avl_st_gen.v. Also I have not found the parent module of e10_avl_st_gen.v, not sure if they visitble for customer?

and not sure how the e10_avl_st_gen.v call the avalon_st_gen without installing it in source code?

I am bit confused about that file.

I have compared them, found the very similar even in sub modules architecture.

many thanks

Jim

Hi,

You can find the module in "eth_e2e_e10/hw/rtl/e10/eth_traffic_controller" directory and "eth_e2e_e10/hw/rtl"

Can I have a call meeintg with you for several minutes? thanks,Jim

[email protected]

May I know what do you want to discuss?

to clarify the question and anwser, because with your anwser I still don not undersdand it clearly

I would recommend you to use Quartus to check the design hierarchy and RTL viewer to see how it is implemented.