Occasional ContributorI have several boards, each has eight FPGAs on them. I'd like to use a PCIe root complex and have each FPGA contain a PCIe switch, and internally, an endpoint. Can someone point me in the right direction to implement this? I have experience in PCIe on Virtex, but this is the first time using Intel.
ContributorHie,
You could start by referring to the Cyclone V PCIe user guide below.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avst.pdf
The example design is available within our Quartus Prime software. Refer to Chapter 2 which describes how to get the example design and its project directory and hierarchy.
Alternatively, you could also refer to the following:
https://rocketboards.org/foswiki/pub/Projects/PCIeRootPort/CV_SoC_PCIe_RP.pdf
Regards,
Nathan
