FPGA DDR memory access before OpenCL aocx loading

Question

Hi all,

We want to access DDR memory of Arria-10 FPGA by OpenCL host code but before the loading of binary image (.aocx).
1. Is it possible to allocate memory when FPGA is just powered on?
2. Can we access DDR banks without .aocx loading and OpenCL kernel execution? We want to copy the data from host to device, device to device through buffers.
3. If yes, can we modify the data before kernel launching, like overwrite the values?
4. Is there any protocol that OpenCL supports for Intel FPGAs, or any devices might support soon?

We'll appreciate your suggestions,

Thanks,
Atul Ghalame

kennyt_altera · Answer

Is that possible that you upgrade to the latest device stratix 10? This platform is going to discontinued.

atul_ghalame · Answer

Hi,
We know this will be discontinued soon but we have to implement our code on the cards we have with us. We would consider next generation devices in future based on what we can achieve with Arria-10 prototype and whether our requirements are being addressed in the latest devices.
Kindly let us know how can we try memory access on current set up of Bittware's A10PL4  &amp; OpenCL 17.1

Thanks,
Atul

hrz · Answer

1. No. Without any firmware/binary loaded onto the FPGA, the PCI-E core will not work and you will not be able to access the FPGA DDR memory. In fact, the FPAG board will not be detected at all in such case. As part of the board setup process, you need to flash the FPGA with a base firmware through JTAG to enable the PCI-E and DDR cores and OpenCL interface. After that, you can access the FPGA DDR memory with or without an .aocx file.
2. If the board has been set up correctly and 'aocl diagnose' passes, yes. All data transfers between host and device are done using host-side API calls. I am not sure what you mean by device to device data transfer, though. If you are trying to move data from one DDR bank on the FPGA board to another DDR bank on the same board, you either have to write a kernel to copy the data through the FPGA (which will require an .aocx file), or you will have to copy the data back to the host and then write it to the other bank.
3. Yes. All data transfer between host and device are initiated from the host side and do not require an active kernel.
4. The question is not clear; what "protocol" are you referring to?

atul_ghalame · Answer

Hi, thanks for your comments,
1. by powered on FPGA, I mean compatible BSP is flashed on the device and library installed on the host machine.  'aocl diagnos'e is able to find the device and run data transfer tests. 
2. Can you provide more on host-side API calls that could transfer host to DDR, DDR to DDR and not necessarily DDR to FPGA on chip memory? We want to copy appropriate data first through our pipeline interface and then load a relevant .aocx image according to metadata. This will provide flexibility to load different designs based on metadata.
3 &amp; 4. Okay, if data transfers between host and device are initiated from the host side, could you point any such examples of API calls/protocol. e.g. data transfer test without loading .aocx

Atul

hrz · Answer

The host-side APIs are standard OpenCL APIs; namely, you can create buffers in the FPGA DDR memory using the clCreateBuffer() API, copy data from host DDR to FPGA DDR using clEnqueueWriteBuffer(), and copy data from FPGA DDR back to host DDR using clEnqueueReadBuffer(). I recommend studying existing OpenCL books/guides since these APIs are common to all OpenCL-capable devices and are not limited to Intel FPGAs.

To perform data transfer from host to device or vice versa, you need to create a "context", then a "queue", then create host buffers using standard C/C++ APIs (malloc or new), then create device buffers using clCreateBuffer(), and then use clEnqueueWriteBuffer() and clEnqueueReadBuffer() to transfer data between host buffers residing in host DDR and device buffers residing in FPGA DDR. None of these APIs depend on a valid "program" or "kernel" and as such, they can all be called without an aocx file.

Slides 54 and onward in the following documentation might be helpful in understanding the flow:
https://extremecomputingtraining.anl.gov/files/2018/08/ATPESC_2018_Track-1_8_7-30_315pm_Moawad-FPGA.pdf

Intel's FPGA SDK for OpenCL guides can also be found below:
https://www.intel.com/content/www/us/en/docs/programmable/683188/21-4/pro-edition-getting-started-guide.html
https://www.intel.com/content/www/us/en/docs/programmable/683846/21-4/overview.html
https://www.intel.com/content/www/us/en/docs/programmable/683521/21-4/introduction-to-pro-edition-best-practices.html

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FPGA DDR memory access before OpenCL aocx loading

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