FPGA DDR memory access before OpenCL aocx loading

1. No. Without any firmware/binary loaded onto the FPGA, the PCI-E core will not work and you will not be able to access the FPGA DDR memory. In fact, the FPAG board will not be detected at all in such case. As part of the board setup process, you need to flash the FPGA with a base firmware through JTAG to enable the PCI-E and DDR cores and OpenCL interface. After that, you can access the FPGA DDR memory with or without an .aocx file.

2. If the board has been set up correctly and 'aocl diagnose' passes, yes. All data transfers between host and device are done using host-side API calls. I am not sure what you mean by device to device data transfer, though. If you are trying to move data from one DDR bank on the FPGA board to another DDR bank on the same board, you either have to write a kernel to copy the data through the FPGA (which will require an .aocx file), or you will have to copy the data back to the host and then write it to the other bank.

3. Yes. All data transfer between host and device are initiated from the host side and do not require an active kernel.

4. The question is not clear; what "protocol" are you referring to?