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Atul_Ghalame's avatar
Atul_Ghalame
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4 years ago

FPGA DDR memory access before OpenCL aocx loading

Hi all, We want to access DDR memory of Arria-10 FPGA by OpenCL host code but before the loading of binary image (.aocx). 1. Is it possible to allocate memory when FPGA is just powered on? 2. ...
KennyT_altera's avatar
KennyT_altera
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4 years ago

Is that possible that you upgrade to the latest device stratix 10? This platform is going to discontinued.


Atul_Ghalame's avatar
Atul_Ghalame
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4 years ago

Hi,

We know this will be discontinued soon but we have to implement our code on the cards we have with us. We would consider next generation devices in future based on what we can achieve with Arria-10 prototype and whether our requirements are being addressed in the latest devices.

Kindly let us know how can we try memory access on current set up of Bittware's A10PL4 & OpenCL 17.1

Thanks,

Atul