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itzmeanjan's avatar
itzmeanjan
Icon for New Contributor rankNew Contributor
4 years ago

FPGA Compile times out even with 24 hours

Hi,

Good day !

I'm using Intel SYCL/ DPC++ for targeting Intel Stratix 10 FPGA on Intel Devcloud, but my current design is somewhat large, so it's taking more time to compile the design. Even when I set `wall_time=24:00:00` in `qsub` command, it doesn't complete by that time.

Is it possible to anyhow set wall_time to higher time span ( say 48:00:00 ) ?

5 Replies

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi itzmeanjan,


    Apologies for the delayed response. Due to previous holiday season we would require some time to run through the situation to understand further and will get back to you as soon as possible (approx. a week/two). Thank you for the patients.


    Thanks.

    Regards,

    Aik Eu


    • itzmeanjan's avatar
      itzmeanjan
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi @aikeu ,

      I've simplified my design such that h/w synthesis time doesn't exceed max walltime, so this is not a problem anymore. Thanks anyway.

      Regards

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi itzmeanjan,


    Good to know that you are able to simplify your design in order to get the compilation done within 24H.

    I will close this thread for now.


    Thanks.

    Regards,

    Aik Eu