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itzmeanjan's avatar
itzmeanjan
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4 years ago

FPGA Compile times out even with 24 hours

Hi, Good day ! I'm using Intel SYCL/ DPC++ for targeting Intel Stratix 10 FPGA on Intel Devcloud, but my current design is somewhat large, so it's taking more time to compile the design. Even w...
itzmeanjan's avatar
itzmeanjan
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4 years ago

Hi @aikeu ,

I've simplified my design such that h/w synthesis time doesn't exceed max walltime, so this is not a problem anymore. Thanks anyway.

Regards