Does a10 transceiver native phy supports 10.3125g datarate when using standard PCS？ how to config it( FPGA 10AX027H4F34I3SG)

Hi,

As I understand it, you have some inquiries related to the 10G data rate support by A10 Native PHY with Standard PCS. For your information, the max data rate supported would be dependent on the core and XCVR speed grade.

As I checked with Native PHY, it seems like the max data rate achievable by your selected part is ~8.9Gbps.

As I tested with part with faster speed grade ie 10AX027H1F34I1HG, the Native PHY is able to achieve the 10.3125Gbps with the Byte SERDES x2 enabled and PCS-PMA interface with = 20 bits.

Please let me know if there is any concern. Thank you.

Thank you so much for your replying, it's very helpful for me.

By the way，I want to download the Arria 10 Transceiver PHY Basic Design Examples "Arria 10 Native PHY PCS direct with rx_pma_clkslip design example Q16.0 (ZIP)" frome Intel Forums (https://forums.intel.com/s/createarticlepage?language=en_US&articleid=a3g0P0000005QkHQAU&action=view ) ​

but it can not be gotten from server, there are no downloading problems with some examples above it. Will you please help to check it? thanks a lot!

Hi,

Thanks for your update. Regarding your latest inquiry on the wiki example design, for your information, the design was stored at wiki page which is no longer accessible. Sorry for the inconvenience.

I have tried to search into the local database and able to find the example design. I have emailed you the ZIP for your reference.

Thank you for your helping, but the attachment is a html file：A10_native_pcs_direct_rxc~1.html‎ (534 B‎) . Will you please email another address tian_xl@126.com ？Sorry to bother you again : )

hi,

I have sent the file to your email. Please let me know if you are still unable to receive it. thank you.