DevCloud: Unable to compile for FPGAs (aoc: Quartus is not on the path!)

Hi, thank you very much for your reply. I have been able to compile my code. However, I still am not able to run it. I have followed your steps to compile but, if I try to run in a "fpga_runtime" node or just "fpga" with the script provided by https://devcloud.intel.com/oneapi/get-started/base-toolkit/#fpga-vector-add-sample-walkthrough I get the error that no device is found:

u36780@login-2:~/BaseKit-code-samples/DPC++Compiler/vector-add$ qsub -l nodes=1:fpga:ppn=2 -d . run_fpga_hw.sh

u36780@login-2:~/BaseKit-code-samples/DPC++Compiler/vector-add$ cat run_fpga_hw.sh.o533282
 
########################################################################
#      Date:           Sat Feb 29 09:04:27 PST 2020
#    Job ID:           533282.v-qsvr-1.aidevcloud
#      User:           u36780
# Resources:           neednodes=1:fpga:ppn=2,nodes=1:fpga:ppn=2,walltime=06:00:00
########################################################################
 
:: setvars has already been run. Skipping any further invocation.  To force its re-execution, pass --force
./vector-add.fpga
Caught a synchronous DPC++ exception:
No device of requested type available. Please check https://software.intel.com/en-us/articles/intel-oneapi-dpcpp-compiler-system-requirements-beta 0 (CL_SUCCESS)
If you are targeting an FPGA hardware, please ensure that your system is plugged to an FPGA board that is set up correctly and compile with -DFPGA
If you are targeting the FPGA emulator, compile with -DFPGA_EMULATOR.
Makefile.fpga:23: recipe for target 'run_hw' failed
 
########################################################################
# End of output for job 533282.v-qsvr-1.aidevcloud
# Date: Sat Feb 29 09:04:29 PST 2020
########################################################################

I have tried both scrips: the run_fpga_hw by default in the documentation and adding paths you provide for compilation with same wrong results:

u36780@login-2:~/BaseKit-code-samples/DPC++Compiler/vector-add$ cat run_fpga_hw.sh
#!/bin/bash
source /opt/intel/inteloneapi/setvars.sh
 
ACDS_ROOT="/glob/development-tools/oneapi/inteloneapi/intelfpgadpcpp/latest/QuartusPrimePro/17.1.1/"
MODELSIM_ROOT="$ACDS_ROOT/modelsim_ae/linuxaloem"
QUARTUS_ROOT="$ACDS_ROOT/quartus"
PATH="$ACDS_ROOT/quartus/bin:$ACDS_ROOT/nios2eds/bin:$MODELSIM_ROOT:.:$PATH"
 
export PATH=$PATH
export QUARTUS_ROOTDIR=$QUARTUS_ROOT
export QUARTUS_HOME=$QUARTUS_ROOT
export LM_LICENSE_FILE=/usr/local/licenseserver/quartus.lic
export ALTERAD_LICENSE=/usr/local/licenseserver/quartus.lic
 
make run_hw -f Makefile.fpga

Am I doing something wrong?

Thanks a lot

Hi,

Now I was able to compile for hardware again.

The previously compiled binaries apparently does not work and it is necessary to recompile then:

u34356@s001-n082:~/oneAPI/Code/mine/adpcm_decoder$ ./adpcm_decoder.fpga
./adpcm_decoder.fpga: symbol lookup error: ./adpcm_decoder.fpga: undefined symbol: _ZN2cl4sycl6detail2pi12piMemReleaseE

Thank you,

Menotti

Hi,

Thank you for your response!

I don't remember seeing the fpga property before, just fpga_compile for nodes with Quartus etc. and fpga_runtime for nodes with FPGA cards, but anyway...

u34356@login-2:~/oneAPI/DPC++Compiler/vector-add$ pbsnodes | grep properties | sort | uniq
     properties = experimental,xeon,clx,ram192gb,net1gbe
     properties = fpga_compile,xeon,plat8153,skl,ram384gb,net1gbe
     properties = fpga_runtime,xeon,gold6128,skl,ram192gb,net1gbe,fpga,arria10
     properties = gen9,xeon,e-2176g,cfl,gpu,ram64gb,net1gbe,6cores,eus0024
     properties = jupyter,batch,xeon,gold6128,skl,ram192gb,net1gbe

I was unable to reproduce your steps on Devcloud, have you done them recently? I tried with the three different properties (removing the -I option that is incorrect when giving a script) and I always get the same error (aoc: Quartus is not on the path!):

u34356@login-2:~/oneAPI/DPC++Compiler/vector-add$ qsub -l nodes=1:fpga:ppn=2 -d . build_fpga_hw.sh
506997.v-qsvr-1.aidevcloud
u34356@login-2:~/oneAPI/DPC++Compiler/vector-add$ qsub -l nodes=1:fpga_compile:ppn=2 -d . build_fpga_hw.sh
506998.v-qsvr-1.aidevcloud
u34356@login-2:~/oneAPI/DPC++Compiler/vector-add$ qsub -l nodes=1:fpga_runtime:ppn=2 -d . build_fpga_hw.sh
506999.v-qsvr-1.aidevcloud
 
u34356@login-2:~/oneAPI/DPC++Compiler/vector-add$ less build_fpga_hw.sh.e*
 
aoc: Quartus is not on the path!
aoc: Is it installed on your system and quartus bin directory added to PATH environment variable?
/home/u34356/tmp/vector-add-63c373.o: file not recognized: File truncated
clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
make: *** [vector-add.fpga] Error 1
/var/spool/torque/mom_priv/epilogue.parallel: line 12: /var/spool/torque/mom_priv/epilogue.d//95-nvdir.epilogue: Permission denied

I also tried to do it interactively with the -I option (note that the allocated nodes are in the intervals you mentioned), but I got the same error:

u34356@login-2:~/oneAPI/DPC++Compiler/vector-add$ qsub -I -l nodes=1:fpga_compile:ppn=2 -d . 
qsub: waiting for job 507000.v-qsvr-1.aidevcloud to start
qsub: job 507000.v-qsvr-1.aidevcloud ready
 
 
########################################################################
#      Date:           Wed Feb 19 09:51:41 PST 2020
#    Job ID:           507000.v-qsvr-1.aidevcloud
#      User:           u34356
# Resources:           neednodes=1:fpga_compile:ppn=2,nodes=1:fpga_compile:ppn=2,walltime=06:00:00
########################################################################
 
u34356@s001-n148:~/oneAPI/DPC++Compiler/vector-add$ make hw -f Makefile.fpga 
dpcpp  -fintelfpga a.o -o vector-add.fpga -Xshardware
aoc: Quartus is not on the path!
aoc: Is it installed on your system and quartus bin directory added to PATH environment variable?
/home/u34356/tmp/vector-add-0ff0ad.o: file not recognized: File truncated
clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
Makefile.fpga:17: recipe for target 'vector-add.fpga' failed
make: *** [vector-add.fpga] Error 1
u34356@s001-n148:~/oneAPI/DPC++Compiler/vector-add$ logout
 
qsub: job 507000.v-qsvr-1.aidevcloud completed
u34356@login-2:~/oneAPI/DPC++Compiler/vector-add$ qsub -I -l nodes=1:fpga_runtime:ppn=2 -d . 
qsub: waiting for job 507003.v-qsvr-1.aidevcloud to start
qsub: job 507003.v-qsvr-1.aidevcloud ready
 
 
########################################################################
#      Date:           Wed Feb 19 09:54:07 PST 2020
#    Job ID:           507003.v-qsvr-1.aidevcloud
#      User:           u34356
# Resources:           neednodes=1:fpga_runtime:ppn=2,nodes=1:fpga_runtime:ppn=2,walltime=06:00:00
########################################################################
 
u34356@s001-n081:~/oneAPI/DPC++Compiler/vector-add$ make hw -f Makefile.fpga 
dpcpp  -fintelfpga a.o -o vector-add.fpga -Xshardware
aoc: Quartus is not on the path!
aoc: Is it installed on your system and quartus bin directory added to PATH environment variable?
/home/u34356/tmp/vector-add-4c2e41.o: file not recognized: File truncated
clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
Makefile.fpga:17: recipe for target 'vector-add.fpga' failed
make: *** [vector-add.fpga] Error 1
u34356@s001-n081:~/oneAPI/DPC++Compiler/vector-add$ logout

Until recently, I compiled several examples using the same scripts / parameters. Since I got the message about --force in the /opt/intel/inteloneapi/setvars.sh script I couldn't do it anymore.

I didn't find Quartus in any of these nodes, what should be the path?

Best regards,

Menotti

Hi,

You also failed to compile for FPGAs and now I realize your mistake. The binary vector-add.fpga does not appear in the output of your ls command, which should be the output of the compilation for FPGA.

You should use the -I option to enter commands interactively or omit it and provide a script, but not both.

When you use the -I option in the qsub command, you open an interactive session on the node to work, but the build_fpga_hw.sh script indicated at the end of the command is ignored.

Thank you,

Menotti

Hi, I have done source /data/intel_fpga/devcloudLoginToolSetup.sh and launched tools_setup. This function allows you to set manually the path to the quartus for different versions. We have tried all the possibilities with no luck. It still fails to compile.

Despite of that, we think we have found some interesting result that may be throw us some light in order to find the solution.

1st option: In this option we set the quartus path the latest version we found in tools_setup.

sourcing /glob/development-tools/versions/intelFPGA_pro/19.3/init_quartus.sh
 
u36780@s001-n082:~/BaseKit-code-samples/DPC++Compiler/vector-add$ make hw -f Makefile.fpga
 
dpcpp -fintelfpga a.o -o vector-add.fpga -Xshardware
 
aoc: Compiling for FPGA. This process may take several hours to complete. Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets. If the reports indicate performance targets are not being met, code edits may be required. Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs.
 
Error (18640): The Quartus Partition Database File '/home/u36780/tmp/a-9fa8e9/build/dcp.qdb' was generated using version 'Version 17.1.1 Build 273 12/19/2017 SJ Pro Edition', which cannot be read by the current version of the Quartus Prime software. Regenerate '/home/u36780/tmp/a-9fa8e9/build/dcp.qdb' using the current version of the Quartus Prime Software.
 
Error (19296): Cannot load none snapshot - ensure the design has been compiled through all earlier stages.
 
Error (19829): dcp.qdb cannot be assigned. The dcp.qdb file is missing Partial Reconfiguration or Reserved Core subpartitions and assigned to the root partition. In order to assign a QDB file to the root partition, it must be created from a design using Partial Reconfiguration or Reserved Core subpartitions. To correct this error, ensure that the creation and assignment of the QDB is correct.
 
Error (18640): The Quartus Partition Database File '/home/u36780/tmp/a-9fa8e9/build/bsp_interface.qdb' was generated using version 'Version 17.1.1 Build 273 12/19/2017 SJ Pro Edition', which cannot be read by the current version of the Quartus Prime software. Regenerate '/home/u36780/tmp/a-9fa8e9/build/bsp_interface.qdb' using the current version of the Quartus Prime Software.
 
Error: Flow failed: 
 
Error: Quartus Prime Synthesis was unsuccessful. 5 errors, 283 warnings
 
Error (23035): Tcl error: 
 
Error (23031): Evaluation of Tcl script compile_script.tcl unsuccessful
 
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
 
Error (23035): Tcl error: 
 
Error (23031): Evaluation of Tcl script build/entry.tcl unsuccessful
 
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
 
Error: Compiler Error, not able to generate hardware
 
 
 
/home/u36780/tmp/vector-add-522df1.o: file not recognized: File truncated
 
clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
 
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
 
Makefile.fpga:17: recipe for target 'vector-add.fpga' failed
 
make: *** [vector-add.fpga] Error 1

The error information appears in line 9:

Error (18640): The Quartus Partition Database File '/home/u36780/tmp/a-9fa8e9/build/dcp.qdb' was generated using version 'Version 17.1.1 Build 273 12/19/2017 SJ Pro Edition', which cannot be read by the current version of the Quartus Prime software. Regenerate '/home/u36780/tmp/a-9fa8e9/build/dcp.qdb' using the current version of the Quartus Prime Software.

Where it says that the build was generated using version 17.1.1 which differs the quartus prime version.

2nd option: We try to compile using this previous version 17.1.

But in this case we get the information error that Intel FPGA SD only support quartus prime versions after 18.1.

sourcing /glob/development-tools/versions/intelFPGA_pro/17.1/init_quartus.sh
 
u36780@s001-n082:~/BaseKit-code-samples/DPC++Compiler/vector-add$ make hw -f Makefile.fpga
dpcpp  -fintelfpga a.o -o vector-add.fpga -Xshardware
aoc: The Intel(R) FPGA SDK for OpenCL(TM) version 19.3api.0 only supports Intel(R) Quartus(R) Prime versions 18.1.0 to 19.3api.0. However, an unsupported Intel(R) Quartus(R) Prime version was found: 
Quartus Prime Shell
Version 17.1.0 Build 240 10/25/2017 Patches 0.03dcp SJ Pro Edition
Copyright (C) 2017  Intel Corporation. All rights reserved.
/home/u36780/tmp/vector-add-2657a2.o: file not recognized: File truncated
clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
Makefile.fpga:17: recipe for target 'vector-add.fpga' failed
make: *** [vector-add.fpga] Error 1

We hope this information will help to find the solution to this issue, allowing us to continue using the FPGA in Intel DevCloud as soon as. posible.

Bests,

I also have the same results..