Forum Discussion
The script suggested above (source /data/intel_fpga/devcloudLoginToolSetup.sh) is usable if you are in interactive mode because it presents you an interactive menu (via tools_setup), but is not useful in batch mode. Additionally, as noted above, the options it gives you do not help because 17.1.1 is not in the options list. The current oneAPI installation that targets Intel Arria 10 FPGA requires version 17.1.1.
As a workaround, you can add additional commands to your build_fpga_hw.sh script. This is explicitly setting up the necessary Quartus environment variables. Here is the full .sh file:
#!/bin/bash
source /opt/intel/inteloneapi/setvars.sh
ACDS_ROOT="/glob/development-tools/oneapi/inteloneapi/intelfpgadpcpp/latest/QuartusPrimePro/17.1.1/"
MODELSIM_ROOT="$ACDS_ROOT/modelsim_ae/linuxaloem"
QUARTUS_ROOT="$ACDS_ROOT/quartus"
PATH="$ACDS_ROOT/quartus/bin:$ACDS_ROOT/nios2eds/bin:$MODELSIM_ROOT:.:$PATH"
export PATH=$PATH
export QUARTUS_ROOTDIR=$QUARTUS_ROOT
export QUARTUS_HOME=$QUARTUS_ROOT
export LM_LICENSE_FILE=/usr/local/licenseserver/quartus.lic
export ALTERAD_LICENSE=/usr/local/licenseserver/quartus.lic
make hw -f Makefile.fpgaWith this updated .sh file, you can now run the compile in batch mode, using the command from the oneAPI Getting Started documentation:
qsub -l nodes=1:fpga_compile:ppn=2 -d . build_fpga_hw.shI will request that Intel addresses this so that the flow is fluid when following the getting started steps.
- JRome286 years ago
New Contributor
Hi, thank you very much for your reply. I have been able to compile my code. However, I still am not able to run it. I have followed your steps to compile but, if I try to run in a "fpga_runtime" node or just "fpga" with the script provided by https://devcloud.intel.com/oneapi/get-started/base-toolkit/#fpga-vector-add-sample-walkthrough I get the error that no device is found:
u36780@login-2:~/BaseKit-code-samples/DPC++Compiler/vector-add$ qsub -l nodes=1:fpga:ppn=2 -d . run_fpga_hw.shu36780@login-2:~/BaseKit-code-samples/DPC++Compiler/vector-add$ cat run_fpga_hw.sh.o533282 ######################################################################## # Date: Sat Feb 29 09:04:27 PST 2020 # Job ID: 533282.v-qsvr-1.aidevcloud # User: u36780 # Resources: neednodes=1:fpga:ppn=2,nodes=1:fpga:ppn=2,walltime=06:00:00 ######################################################################## :: setvars has already been run. Skipping any further invocation. To force its re-execution, pass --force ./vector-add.fpga Caught a synchronous DPC++ exception: No device of requested type available. Please check https://software.intel.com/en-us/articles/intel-oneapi-dpcpp-compiler-system-requirements-beta 0 (CL_SUCCESS) If you are targeting an FPGA hardware, please ensure that your system is plugged to an FPGA board that is set up correctly and compile with -DFPGA If you are targeting the FPGA emulator, compile with -DFPGA_EMULATOR. Makefile.fpga:23: recipe for target 'run_hw' failed ######################################################################## # End of output for job 533282.v-qsvr-1.aidevcloud # Date: Sat Feb 29 09:04:29 PST 2020 ########################################################################I have tried both scrips: the run_fpga_hw by default in the documentation and adding paths you provide for compilation with same wrong results:
u36780@login-2:~/BaseKit-code-samples/DPC++Compiler/vector-add$ cat run_fpga_hw.sh #!/bin/bash source /opt/intel/inteloneapi/setvars.sh ACDS_ROOT="/glob/development-tools/oneapi/inteloneapi/intelfpgadpcpp/latest/QuartusPrimePro/17.1.1/" MODELSIM_ROOT="$ACDS_ROOT/modelsim_ae/linuxaloem" QUARTUS_ROOT="$ACDS_ROOT/quartus" PATH="$ACDS_ROOT/quartus/bin:$ACDS_ROOT/nios2eds/bin:$MODELSIM_ROOT:.:$PATH" export PATH=$PATH export QUARTUS_ROOTDIR=$QUARTUS_ROOT export QUARTUS_HOME=$QUARTUS_ROOT export LM_LICENSE_FILE=/usr/local/licenseserver/quartus.lic export ALTERAD_LICENSE=/usr/local/licenseserver/quartus.lic make run_hw -f Makefile.fpgaAm I doing something wrong?
Thanks a lot
- Shawn_S_Intel6 years ago
Occasional Contributor
You certainly aren’t doing anything wrong. Once my compilation completed I also realized that the execution on the FPGA HW is not executing. As far as I can tell, the node setup seems to have changed such that the setup of the driver and/or the OpenCL BSP is not in order.
I’ve reached out to some folks that are closer to the devcloud node maintenance than I am. Hopefully it can be resolved soon. In the meantime, thanks for your continued patience.