DevCloud: Unable to compile for FPGAs (aoc: Quartus is not on the path!)

Hi, I have done source /data/intel_fpga/devcloudLoginToolSetup.sh and launched tools_setup. This function allows you to set manually the path to the quartus for different versions. We have tried all the possibilities with no luck. It still fails to compile.

Despite of that, we think we have found some interesting result that may be throw us some light in order to find the solution.

1st option: In this option we set the quartus path the latest version we found in tools_setup.

sourcing /glob/development-tools/versions/intelFPGA_pro/19.3/init_quartus.sh
 
u36780@s001-n082:~/BaseKit-code-samples/DPC++Compiler/vector-add$ make hw -f Makefile.fpga
 
dpcpp -fintelfpga a.o -o vector-add.fpga -Xshardware
 
aoc: Compiling for FPGA. This process may take several hours to complete. Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets. If the reports indicate performance targets are not being met, code edits may be required. Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs.
 
Error (18640): The Quartus Partition Database File '/home/u36780/tmp/a-9fa8e9/build/dcp.qdb' was generated using version 'Version 17.1.1 Build 273 12/19/2017 SJ Pro Edition', which cannot be read by the current version of the Quartus Prime software. Regenerate '/home/u36780/tmp/a-9fa8e9/build/dcp.qdb' using the current version of the Quartus Prime Software.
 
Error (19296): Cannot load none snapshot - ensure the design has been compiled through all earlier stages.
 
Error (19829): dcp.qdb cannot be assigned. The dcp.qdb file is missing Partial Reconfiguration or Reserved Core subpartitions and assigned to the root partition. In order to assign a QDB file to the root partition, it must be created from a design using Partial Reconfiguration or Reserved Core subpartitions. To correct this error, ensure that the creation and assignment of the QDB is correct.
 
Error (18640): The Quartus Partition Database File '/home/u36780/tmp/a-9fa8e9/build/bsp_interface.qdb' was generated using version 'Version 17.1.1 Build 273 12/19/2017 SJ Pro Edition', which cannot be read by the current version of the Quartus Prime software. Regenerate '/home/u36780/tmp/a-9fa8e9/build/bsp_interface.qdb' using the current version of the Quartus Prime Software.
 
Error: Flow failed: 
 
Error: Quartus Prime Synthesis was unsuccessful. 5 errors, 283 warnings
 
Error (23035): Tcl error: 
 
Error (23031): Evaluation of Tcl script compile_script.tcl unsuccessful
 
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
 
Error (23035): Tcl error: 
 
Error (23031): Evaluation of Tcl script build/entry.tcl unsuccessful
 
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
 
Error: Compiler Error, not able to generate hardware
 
 
 
/home/u36780/tmp/vector-add-522df1.o: file not recognized: File truncated
 
clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
 
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
 
Makefile.fpga:17: recipe for target 'vector-add.fpga' failed
 
make: *** [vector-add.fpga] Error 1

The error information appears in line 9:

Error (18640): The Quartus Partition Database File '/home/u36780/tmp/a-9fa8e9/build/dcp.qdb' was generated using version 'Version 17.1.1 Build 273 12/19/2017 SJ Pro Edition', which cannot be read by the current version of the Quartus Prime software. Regenerate '/home/u36780/tmp/a-9fa8e9/build/dcp.qdb' using the current version of the Quartus Prime Software.

Where it says that the build was generated using version 17.1.1 which differs the quartus prime version.

2nd option: We try to compile using this previous version 17.1.

But in this case we get the information error that Intel FPGA SD only support quartus prime versions after 18.1.

sourcing /glob/development-tools/versions/intelFPGA_pro/17.1/init_quartus.sh
 
u36780@s001-n082:~/BaseKit-code-samples/DPC++Compiler/vector-add$ make hw -f Makefile.fpga
dpcpp  -fintelfpga a.o -o vector-add.fpga -Xshardware
aoc: The Intel(R) FPGA SDK for OpenCL(TM) version 19.3api.0 only supports Intel(R) Quartus(R) Prime versions 18.1.0 to 19.3api.0. However, an unsupported Intel(R) Quartus(R) Prime version was found: 
Quartus Prime Shell
Version 17.1.0 Build 240 10/25/2017 Patches 0.03dcp SJ Pro Edition
Copyright (C) 2017  Intel Corporation. All rights reserved.
/home/u36780/tmp/vector-add-2657a2.o: file not recognized: File truncated
clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
Makefile.fpga:17: recipe for target 'vector-add.fpga' failed
make: *** [vector-add.fpga] Error 1

We hope this information will help to find the solution to this issue, allowing us to continue using the FPGA in Intel DevCloud as soon as. posible.

Bests,