create_generate_clock

If my source clock pass two PLL and new clock divided 3 to create new clock, how do I use create_generate_clock?

Since Altera used derive_pll_clocks, it little bit confuse me now. I think It should do in the last stage to use create_generate_clocks because Altera has variable erive_pll_clocks, so the -source [clock_pin] should be the first drive pll pin, am I correct?

Thanks,

-Fred