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Occasional Contributor

6 years ago

create_generate_clock

If my source clock pass two PLL and new clock divided 3 to create new clock, how do I use create_generate_clock? Since Altera used derive_pll_clocks, it little bit confuse me now. I think It should ...

Rahul_S_Intel1

Frequent Contributor

6 years ago

Hi,

Kindly find the places wwhere create_generate_clock is been used

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/timinganalyzer/clocking/tq-generate-clock.html

fxu001
Occasional Contributor
6 years ago
Hi RSree Which value should I set for the JESD204B input and output ports as following Snipping . Please give ASAP [cid:e99ad932-779a-4345-bcae-8419d3353521] [cid:7a289d19-bc51-483b-a1ef-410d353a6a2a] Thanks, -Fred

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create_generate_clock

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