Forum Discussion
fxu001
Occasional Contributor
Occasional Contributorcreate_generate_clock
If my source clock pass two PLL and new clock divided 3 to create new clock, how do I use create_generate_clock? Since Altera used derive_pll_clocks, it little bit confuse me now. I think It should ...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi,
Kindly find the places wwhere create_generate_clock is been used
https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/timinganalyzer/clocking/tq-generate-clock.html
fxu001Hi RSree Which value should I set for the JESD204B input and output ports as following Snipping . Please give ASAP [cid:e99ad932-779a-4345-bcae-8419d3353521] [cid:7a289d19-bc51-483b-a1ef-410d353a6a2a] Thanks, -Fred
