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RN1's avatar
RN1
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3 years ago

Cannot compile with Stratix10 in DevCloud and Attributes-Local Memory Performance

Hi, ==== First part) Stratix10 ==== We tried different ways without luck, therefore, we attach the same steps using the interactive session in a fpga_compile machine. We tried directly with you...
BoonBengT_Altera's avatar
BoonBengT_Altera
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3 years ago

Hi @RN1,

Thank you for posting in Intel community forum and hope all is well.

For the first part of the example, my guess is that the node using (i.e. s001-n057) does not have the required hardware. You can check the nodes spec via pbsnodes to get more information on the node.

Would recommend to use the nodes with S10 oneapi, however current there are some error going on the nodes and it has been escalated to the required team.

On the second part, there are optimization guide to programming with oneAPI as well as existing match library as below which would be a good recommended way to start with which we are looking into your mention code:

- https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/software-development-process/performance-tuning-cycle/optimize.html

- https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/api-based-programming/intel-oneapi-math-kernel-library-onemkl.html

Hope that clarify.

Best Wishes

BB

  • RN1's avatar
    RN1
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi @BoonBengT_Altera

    Thanks. Regarding the node, we achieved to compile in the s10 oneapi as you suggested, but the performance is really low compared with OpenCL.

    Thanks, but we have checked previously those links, and they say nothing regarding local memory optimizations. You have the code in the previous post, and you have here the reports that we have extracted, maybe you know what to do to increase the performance since it is still quite slower compared with the OpenCL version.

    I attach the captures and reports as a file.


    It is compiled like this:

    dpcpp -fintelfpga -Xshardware -fsycl-link=early -Xsfp-relaxed=true -Xsno-interleaving=default -Xsno-interleaving=DDR -Xsno-accessor-aliasing block_matrix_mul_dpcpp.cpp

    Thanks for your time.