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jAqui8's avatar
jAqui8
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6 years ago

Altera PLL (cycloneV) getting locked to the wrong frequency.

I have generated a PLL with dynamic reconfiguration enabled.

Ref frequency = 160 MHz,

Target Frequency = 16 MHz.

before lock

reconfig_to_pll[63:0] = 0_3c000000

reconfig_to_pll[63:0] = 0_3c000001

after lock

reconfig_to_pll[63:0] = 0_10000003

reconfig_to_pll[63:0] = 0_10000002

It changes every half cycle of ref clk.

But after reset PLL is getting locked to 105.77 MHz. Though I am expecting it to get locked to 16 MHz. Is this behavior expected?

For experiment : I generated a PLL for 50 MHz ref clk . Target frequency 16 MHz. It is getting locked to correct frequency.

Attaching snapshot of the PLL behavior for 160 MHz ref_clk.

PS: Altera-pll ip core user guide doesn't give information about reconfig_to_pll signal. Please direct me to correct document.

3 Replies

  • jAqui8's avatar
    jAqui8
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi Rsree,

    Thanks for the reply!

    I have followed that document.

    I think the problem is with PLL IP. I tried generating PLL for reference frequency- 50 , 100, 105, 110, 160 MHz.

    for fref 50 MHz : f tareget = 16 MHz --- PLL locked to ~16 MHz

    for fref 100 MHz : f tareget = 16 MHz --- PLL locked to ~16 MHz

    for above 100 MHz, ---pll is locking to some random frequency after reset.

    PS: in all the above cases, the dynamic reconfiguration was enabled and connection between pll ip and reconfiguration block was made as per an661 document.

    Regards,

    Jawed

    • Rahul_S_Intel1's avatar
      Rahul_S_Intel1
      Icon for Frequent Contributor rankFrequent Contributor
      6 years ago

      Hi ,

      The above behavior is wired, I have you check the below . Or any glitch in the input

      Are the RREF pins connected correctly with its own individual resistor to GND

      Are VREF and termination of the I/O standards set correctly?