Altera PLL (cycloneV) getting locked to the wrong frequency.

Hi Rsree,

Thanks for the reply!

I have followed that document.

I think the problem is with PLL IP. I tried generating PLL for reference frequency- 50 , 100, 105, 110, 160 MHz.

for fref 50 MHz : f tareget = 16 MHz --- PLL locked to ~16 MHz

for fref 100 MHz : f tareget = 16 MHz --- PLL locked to ~16 MHz

for above 100 MHz, ---pll is locking to some random frequency after reset.

PS: in all the above cases, the dynamic reconfiguration was enabled and connection between pll ip and reconfiguration block was made as per an661 document.

Regards,

Jawed