Forum Discussion
jAqui8
New Contributor
New ContributorAltera PLL (cycloneV) getting locked to the wrong frequency.
I have generated a PLL with dynamic reconfiguration enabled. Ref frequency = 160 MHz, Target Frequency = 16 MHz. before lock reconfig_to_pll[63:0] = 0_3c000000 reconfig_to_pll[63:0] = 0_3c00000...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
Can you please try to follow the below PLL reconfiguration document.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an661.pdf
