Most RecentAre there any known issues with the transceiver Tx signal integrity that may increase the BER on Stratix® V GX production silicon devices?Why does aocl diagnose fail on Ubuntu 16.04 (kernel 4.14 or newer)?Why does the GTS JESD204B IP Design Example in Dual Simplex PHY only mode remain in the reset state when simulating with the VCSMX simulation tool?Why cannot I access the link pointing to the pll_locked_soft_logic.zip file in the Arria® II GX FPGA and Stratix® IV GX FPGA errata sheet ?Why does the transceiver pll_locked signal deassert when rx_analogreset is asserted during simulation of Cyclone® IV GX devices?Why do I get Old Data reported when the Read During Write in True-Dual-Port RAM is set to New Data?Why might the PCI Express signal detect feature fail at low temperatures on Arria® V GT and ST devices, and the link fails to train?Internal Error: Sub-system: PVAFAM_VISITOR, File: /quartus/power/pvafam/pvafam_titan_atom_visitor_main.cpp, Line: 2002 Atom type not supported by PVAHow do I enable programming file generation support for EP4CGX30CF23, EP4CGX50CF23, EP4CGX50DF27, EP4CGX75CF23 and EP4CGX75DF27 commercial and industrial grade devices in Quartus® II software version 10.1 SP1?Why does the Arria® II GX transceiver CDR, configured in automatic locked mode, keeps the rx_freqlocked signal asserted in any other mode except PCIe mode?
