Most RecentWhy does the ALTLVDS_TX megafunction generate tx_outclock incorrectly when using a serialization factor of 3?Simulation Example Design Fails and Produces WarningsWhy is data corrupted when performing loopback using the Arria 10 Hard IP for PCI Express in Gen1 and Gen2 modes?What is the output register option in DCFIFO megafunction?Error(18694): The reference clock on PLL "external_pll|external_pll|altera_iopll_i|c10gx_pll|iopll_inst", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pQsys Error: no modules found when analyzing nullUnsupported Ports in Arria 10 Native Fixed Point DSP IP Core for m18x18_full and m27x27 Operation ModesWhy have unused ports appeared on the Triple Speed Ethenet (TSE) IP in Quartus II software version 13.0?Why am I experiencing compilation failures with the F-Tile Ethernet Hard IP design when the Ethernet mode is set to 25GE-1 variant and the FEC mode is configured as IEEE 802.3 RS(544,514)?Why do I get "Error (21596): Target device at device index 1 does not support CONFIG status report." when I try to run the configuration status report using the quartus_pgm command?
