Recent Discussions
Quartus II 14.0 (64bit) - vsim error 3170 - Could not find test vector
Hello, I'm a rookie user of Quartus II suite and an entry-level VHDL developer. After creating a project in which I used an Altera IP megafunction (a shift register), the University Program VWF won't work again. It states: "Error: (vsim-3170) Could not find 'work.SIMPLEADDER_vlg_vec_tst'." I'm writing code in VHDL, but I noticed that every time I try running a RTL simulation in University Program VWF the EDA Tool Format Setting switches to Verilog HDL by itself, whereas I select VHDL prior to beginning the simulation. Does anybody have an idea about what is the problem? Consider that I was able to simulate without issues before creating and trying to simulate one project with an IP component. Thank you in advance.
FPGA Monitor Program 18.1 Tutorial: Could not query JTAG Instance IDs. Please ensure the FPGA has be
Greetings, I have been following the instructions in "Intel FPGA Monitor Program Tutorial for ARM.pdf" with "Intel FPGA Monitor Program" version 18.1 to work with the board DE10-Nano. The result was not successful. Please find appended below the transcript of the "Info&Errors". Please also find attaches a series of screen capture of the process following the instructions from the above said tutorial documentation. Please advise if I missed something. Please advise if you need more screen captures. Regards, phiho Writing the makefile: F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/makefile cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make clean make: *** No rule to make target `clean'. Stop. Writing the makefile: F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/makefile cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make clean make: *** No rule to make target `clean'. Stop. G:/intel/FPGA/Lite/18.1/quartus/bin64/quartus_pgm -c "DE-SoC [USB-1]" --auto 1) DE-SoC [USB-1] 4BA00477 SOCVHPS 02D020DD 5CSEBA6(.|ES)/5CSEMA6/.. Info: ******************************************************************* Info: Running Quartus Prime Programmer Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition Info: Copyright (C) 2019 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Sat Jan 23 04:28:56 2021 Info: Command: quartus_pgm -c "DE-SoC [USB-1]" -m jtag -o P;G:/intel/FPGA/Lite/18.1/University_Program/Computer_Systems/DE10-Nano/DE10-Nano_Computer/verilog/DE10_Nano_Computer.sof@2 Info (213045): Using programming cable "DE-SoC [USB-1]" Info (213011): Using programming file G:/intel/FPGA/Lite/18.1/University_Program/Computer_Systems/DE10-Nano/DE10-Nano_Computer/verilog/DE10_Nano_Computer.sof with checksum 0x0B07E6FB for device 5CSEBA6U23@2 Info (209060): Started Programmer operation at Sat Jan 23 04:29:01 2021 Info (209016): Configuring device index 2 Info (209017): Device 2 contains JTAG ID code 0x02D020DD Info (209007): Configuration succeeded -- 1 device(s) configured Info (209011): Successfully performed operation(s) Info (209061): Ended Programmer operation at Sat Jan 23 04:29:04 2021 Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4465 megabytes Info: Processing ended: Sat Jan 23 04:29:04 2021 Info: Elapsed time: 00:00:08 Info: Total CPU time (on all processors): 00:00:04 cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make clean make: *** No rule to make target `clean'. Stop. cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make compile make: *** No rule to make target `compile'. Stop. cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make compile make: *** No rule to make target `compile'. Stop. Could not query JTAG Instance IDs. Please ensure the FPGA has been configured using the correct .sof file.WORKING: DE2-115 Simple Socket Server
Hi, It seems difficult to get help on these forums so I want to pass on what i learnt for others. I've struggled to learn FPGAs over the past few weeks and I have finally got a simple socket server working for the DE2-115. I'll quickly post my findings so someone else can take this and learn from it and not have to struggle on their own as i did. procedure I'll make this brief: I used updated versions for everything as of 4/4/11. 10.1 Sp1. Download and install the Knowledge base update to prevent nios from crashing. http://www.altera.com/support/kdb/solutions/rd12222010_317.html Take the Quartus DE2_115 webserver example for Enet0 RGMII that comes on the CD and use quartus flash programmer to program. Get this PDF and follow its instructions "http://www.altera.com/literature/tt/tt_nios2_tcpip.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=simple socket server example nios edition socket server example nios edition" NOTE it includes the spaces (wierd). do everything the same except the part mentioned in my next step. Instead of copying the files from the tutorial.zip; copy the ones that i have attached to this post. (the .c and .h files including the eeprom folder) This example will now work as explained in the pdf. explanation The original example code in the tutorial does not have the correct method for gettig the MAC address on the DE2-115. I have deleted the majority of the original MAC code and replaced it with code i got from the DE2-115 webserver example. This includes the flashgetoffset function. The LED_PIO_BASE in the original is an invalid for the DE2-115. I replaced it with the LEDG (green leds), you could replace it with red if you wished. This has been done by modifying the led.c file. Sorry for the quick rush post, but i truly hope this helps someone. We should all try to help each other and I hope over the coming months that someone does the same for me with any problems i get in the future. Any questions just ask
Problem when trying to compile a project after downloading the full quartus prime with modelsim included
couldn't open "transcript": permission denied # Reading C:/intelFPGA/19.1/modelsim_ase/tcl/vsim/pref.tcl # Trace back: ** Error: (vlib-35) Failed to create directory "C:/intelFPGA/19.1/work". # Permission denied. (errno = EACCES) # child process exited abnormallySimple Socket Server on DE2 w/Davicom DM9000A
updated. Altera's Simple Socket Server demo running on a DE2 board with the Davicom DM9000a driver. here it is....zipped downloaded project source for sss on the de2 board. download link currently unavailable. Includes: - Hardware design (TLD in schematic block diagram format) - Programmable .SOF (time-limited, as developed in Quartus Web Edition v9.2) - SOPC builder system file - DM9000A driver for Nichestack TCP/IP stack / Altera HAL environment (courtesy of Columbia Uni) - Simple socket server software Simply... - (1) Download the .SOF in Quartus Programmer - (2) Open the software workspace in the "/software" directory in Nios II Build Tools (Eclipse IDE) - (3) Open Run >> Run Configurations. Delete the current configuration. Create a new launch configuration selecting the project name under the Project Tab. Ensure your DE2 board is plugged into USB. Check the target connection tab and make sure it is present. - (4) Plug into your local network (DHCP is enabled, or app will default to static IP) - (5) View the Nios II console for debugging information (via JTAG UART) - (6) Telnet into the board from a pc: telnet <ip address> 30. Enjoy the simple socket server demo from Altera! Questions/comments? Fire away below!
GPIO Pin Problems
Hi all, I am attempting to interface an ultrasonic range sensor with the DE2 board through the GPIO expansion header. The device has 4 connections, 5v vcc, ground, trigger, and echo. The 5v and ground have been attached to the appropriate power supply pins as indicated in the manual and I'm trying to connect the trigger and echo to a couple of the other pins - say GPIO[0] AND GPIO[1]. The project at this point is being built from scratch rather than coded in VHDL or Verilog, to our detriment, as we are still barely scratching the surface of using the languages. I have build circuitry that should function properly but I'm hitting a roadblock when it comes to actually getting input and output through the pins for some reason. Right now I have a basic test project trying to resolve the issue - please see attached image. Problem# 1: With the .qsf file we have at the school the GPIO pin assignments are completely missing! Unless they are renamed something other than what's in the manual. That same .qsf file has been working fine all year. I went to altera support to try downloading a newer version but the link doesn't seem to be working properly in edge browser or firefox. Problem# 2: When I try using the 14 pin general purpose IO connector instead it seems to make the assignments, because at least they exist in the .qsf file, but when I compile and program the board the results are way off base. The pin EX_IO[0] doesn't respond at all to SW[0] being toggled - a voltmeter measures no change between the pin and ground. Then pin EX_IO[1], which was supposed to light up LEDR[0] when a voltage was detected is outputting a steady 3.3v even though assigned as an input pin, and LEDR[0] is lit up constantly. Also, segment 1 of HEX2 display is lit up for no discernible reason. I'm coming to the unfortunate conclusion that I have no idea what I'm doing when it comes to using these IO pins and would greatly appreciate any help for this new user. Please assume I know nothing and point me in the right direction. I'm comfortable with a lot of the concepts of digital logic design and I'm comfortable doing research if maybe someone could help me find the right search terms to use. I've been attempting to research this for two days without any breakthroughs. Thanks in advance for any help. Using: Quartus Prime Lite Windows 10 64 bit DE2 board: EP4CE115F29C7N
