Most Recenthow can I write a code with an input or an output of type double or float??How to fix BDF Text Scaling Bug when Windows Scaling active?Hi, i am having this error and I don't know how to fix it, I have to finish this for today for my school and I do not know what to do. Error (10170): Verilog HDL syntax error at ctrl.v(170) near text: "assign"; expecting an operand.can we use the license of Quartus pro in the Quartus standard ver ? if yes them how can we use cyclone v in std ver?I am studying on VHDL language with ISE Design Suite 14.7 (Basys-2 board). And I want to design 8 bit Register (PC), (it has several conditions these are below).I am unable to download Quartus Prime Pro 19.4 and Standard 19.1 combined files or any kind of FPGA software files. I am logged in but clicking on the download blue button doesn't do any thing. My net speed is good. Issue is with only Altera FPGA softwareI can't install devices (Quartus 17.0 prime lite edition)VSIM 3033 (MODELSIM ALTERA) ERROR FFT IP COREGetting Synthesis Error due to undefined Macros In quartus pro 18.0Can I change weak pull up status of a FPGA pin during runtime?
