New ContributorGetting Synthesis Error due to undefined Macros In quartus pro 18.0
Hi, Observing an error in quartus,
Info: *******************************************************************
Info: Running Quartus Prime Synthesis Info: Version 18.0.0 Build 219 04/25/2018 Patches 0.06 SJ Pro Edition
Info: Processing started: Wed Mar 25 05:18:11 2020
Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off for_generate -c for_generate Info: qis_default_flow_script.tcl version: #1
Info: Initializing Synthesis... Info: Project = "for_generate"
Info: Revision = "for_generate" Info: Analyzing source files
Critical Warning(13432): Verilog HDL Compiler Directive warning at for_gen.sv(19): text macro "ONE" is undefined
Error(13411): Verilog HDL syntax error at for_gen.sv(19) near text ; Error(13363): Verilog HDL error at for_gen.sv(23): module "for_gen" ignored due to previous errors
Error: Flow failed: Error: Quartus Prime Synthesis was unsuccessful. 3 errors, 1 warning
Code:
module for_gen
#(parameter SIZE = 8) ( input [SIZE-1:0] gray, output [SIZE-1:0] bin ); localparam bit ON=1'b0;
genvar gi; // generate and endgenerate is optional generate
for (gi=0; gi<SIZE; gi=gi+1) begin : genbit
if(ON == 1'b1) begin
assign bin[gi] = ^gray[SIZE-1:gi]; // Thanks Dhruvkumar! end else begin assign bin[gi] = `ONE;
end
end
endgenerate
endmodule
I have declared `ONE in one of the include file and its part of project added in qsf as
set_global_assignment -name VERILOG_INCLUDE_FILE "/nfs/site/disks/dcsg_0041/sumukhbn/for_generate/include/for_gen_inc.vh"
But why still I am seeing this error?
Please resolve as soon as possible
