Forum Discussion
New ContributorGetting Synthesis Error due to undefined Macros In quartus pro 18.0
Regular ContributorHi,
In the link provided, the code itself can pass compilation with and without 'include "macro.v" becuase it doesnt use the content defined in macro.v in the and_op.v.
The Intel Quartus Prime Pro Edition synthesis uses a different method to define the compilation unit. It follows the Single-file compilation unit (SFCU) method to select compilation unit files. In SFCU, each file is a compilation unit. Items visible only in the compilation-unit scope include macros, global declarations, and default net types. Therefore, you have to add `include in the main.v file.
Thanks.
Best regards,
KhaiY
New ContributorHi,
You are right, in the image attached include file is not required but if you read the explanation below 2 lines are mentioned.
- We need to add the include (macro)files to the project and just compile for Quartus STD & LITE.
- For Quartus Pro, the compiler to search for macro file and include it during the compile process. No need to use `include in Verilog module. Please check the attached image
Similar to this I found one more query related to this
https://forums.intel.com/s/question/0D50P00003yyT6uSAE/unable-to-synthesize-the-design-with-macros-and-header-files-due-to-undefined-macros?language=en_US
please check on this.
It will be good if you can come back on solution as soon as possible.
