Most RecentExporting .stp file to csv filePath delay between two netsHow to Set the Output Delay of the Arria 10 I/OSpeeding up Quartus P&R in the cloud[Qsys] LPDDR2 Controller (UniPHY): HDL generation fails.Qsys 18.1 automatic ip generation not workingFeedback return path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 is not of the recommended typeHow to include user vhdl defined package in ModelSim-Altera RTL Simulation?Incremental compilation for transceiver (HSSI) on Cyclone 10 and Arria 10I'm a teacher , teaching programmable IC's (CPLD and FPGA). We have a testboard with the Altera MAX and the Flex 10K (EPF10K70RC240-4), from 2002.
