New ContributorHi guys, I am new to fpga development and I have a question regarding qsys 18.1 ip generation.
When using qsys 17 the function "qsys-generate" works great. However, qsys 18's "qsys-generate" is not enough. The pnr process fails because no ip files were generated. How can I use cli to generate all needed files from a .qsys file?
Thank you guys!
Super ContributorThis seems to be a bugs to me, can you attached your qsys files for us to have a look? Attached two qsys files, one is 17 and another is 18.1
Super ContributorAny update?
New ContributorThank you for answering.
unfortunately I can't upload the qsys file since it is company property.
However the qsys is very simple and only has 1 ip core so I don't think this is case specific.
p.s. Do you know how to generate a _hw.tcl file in quartus 14.0 from a .qsys file using linux cli?
Super ContributorWe can sign up an NDA and we can work offline on this. You may check your email for details.
New ContributorAs I said before, the qsys is very simple and only has the i2c ip core. So I think we don't need an NDA I just can't upload the qsys.
Could you please explain the normal way to generate the required ip cores from a qsys file?
Thank you again.
Super ContributorJust go to platform designer to create the i2C ip cores, I will attached the design.qar here. Let me know the steps that you had used where your pnr process failed.
Super ContributorIf you can attached you simplified project.qar, it would be great.
Super Contributorany update?
