Most RecentIssue programming 2 MAX 10 devices over JTAG using STAPL software.ALTDDIO - 16bitx250MHz to 32bitx125MHz - Proper Timequest timing closure?Cyclone V DDR3 package deskewMT25Q 1G supported ?Your web page link for obtaining a MAX PLUS license using hard disk ID is brokenHow can I set the DFE (Decision Feedback Equalization) in Adaptive Mode for the 10G transceivers inside Cyclone 10 GX?Flash memory for Cyclone V-GX.Basic VHDL arithmetic not working on std_logic_vectors in Altera (vs Xilinx)Hey all, i'm designing a board using cyclone 10 GX, i'm using the Altera evaluation kit as reference. only one available.EMIF TOOLKIT failure, see screenshot. Added Hard Memory controller to design, but calibration results show a failure in the EMIF toolkit. what is the source of the error?
