Most RecentI can successfully run the design example from PCIe IP guide for A10 devkit, however when I exchang the onchip_memory2_0 component with my own it hangs the PCIe bus.请问，FPGA的差分ClK引脚，p管脚用作单端时钟输入或输出了，n管脚可否用作普通I/O，还是必须空着？如果不用空着，是否需要接地？谢谢I am trying to follow the DE10 Standard My_First_HPS guide to do the "Hello World!" example shown. I am having a error when I am trying to compile the Makefile. Firstly, I have write "make -f Makefile.mk" and I get "make: *** [my_first_hps] Error 193".partial reconfig process, when program the pr rbf to fpga through JTAG, it failedhow can we start quartus ii std version in linux version by command..Arria V Starter kit installation softwareWhether single port IO and LVDS can be in the same bank in S10？Routing rule of LVDShow to add EPM2210GF256C3 to device list in quartus II rev.14voltage toleration for the high Z state
