Routing rule of LVDS

Question

Hi expertsWhat's the routing rule of LVDS? For example, differential pair’s intra length matching, Clock-to-Data length matching, maximum trace length, etc.Or any guide for reference?

rahul_s_intel1 · Answer

Hi , I am kindly requesting to follow the guidelines provided by alterahttps://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/board-design-guidelines.html

rahul_s_intel1 · Answer

Hi , Kindly let me know if you need further assistance

Forum Discussion

Routing rule of LVDS

2 Replies

Recent Discussions

MAX10 10M50 Development KIT Triple Speed Ethernet problem

About PCIe Daughter Cards for Agilex™ 3 FPGA and SoC C‑Series Development Kit

Stratix 10 FPGA Dev Kit VCCIO_FMC voltage issue

Stratix 10 Development Kit HiLo connector

Technical Assistance Request for Stratix® 10 SX SoC Development Kit (so#488775)