Most RecentI have generated an example design for PCIe , which is targeted for Stratix 10 DX development kit. I tried the simulation on Modelsim PE edition with scripts generated by Quartus pro. Attached error of simulation. please help fix the issue.Why is the reslut of 18.1 standard and pro for migration device difference?What's the max toggle rate of single-end LVTTL and LVCOMS IO of Max10?Received a new 10M08 Evaluation Kit from DigiKey. The instruction blurp with the board says to plug it into USB connector and the 5 red LEDs should flash. When I plug it in, the red LEDs come on and stay that way (no flashing). The green LED also comes onALTERA Scatter-Gather DMA coreHow does FPGA reconfigures if it doesn't use nCONFIG pin in Arria V FPGA?How to configure the UART-Usb port in a DE1 SOC fpga??在C10GX中的DDR3 IP avalon 位宽如何修改？Cyclone10のCORE電圧に1.1Vを印加するとどんな不具合を引き起こしますかRoHS exemption 15 expiring on 02/29/2020
