ArthurDent
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Re: ModelSim INTEL FPGA STARTER EDITION supports only one user on linux
Hi Nurina, thank you for your reply. The " ModelSim - Intel FPGA Edition Software License" cost 2000 USD, and it might not be possible to run "ModelSim - Intel FPGA Edition" and "ModelSim - INTEL FPGA STARTER EDITION" simultaneous. Another possibility is to install "ModelSim - INTEL FPGA STARTER EDITION" on two different machines. BR AD3.5KViews0likes0CommentsRe: ModelSim INTEL FPGA STARTER EDITION supports only one user on linux
Hi Nurina We have also "ModelSim ALTERA STARTER EDITION vsim 10.5b " installed, but it is not used. The design simulates fine when no other users use vsim so it doesn't seem to be a line number issue. The first users have no problems launching and running simulation. Yes, it is not connected to a specific user. If the first user only starts the ModelSim GUI and are not running a simulation, then the second user can use ModelsIm without any issues. If the first user has an active simulation, then the second user is kicked out after 5 min with "** Fatal: vsimk is exiting with code 4." BR AD3.6KViews0likes0CommentsModelSim INTEL FPGA STARTER EDITION supports only one user on linux
Hi We are using Quartus Prime Lite 20.1 .1 which includes Model Technology ModelSim - INTEL FPGA STARTER EDITION vsim 2020.1 . The tools are installed on a linux (CentOS 7) server which is the main development platform. The problem is that ModelSim INTEL FPGA STARTER EDITION only supports one user: - The first user that starts ModelSim can run simulations without any issues - Other users can run simulation for 5 minutes before ModelSim terminates with "Fatal: vsimk is exiting with code 4". Exit code 4 seems to be a license issue code. Sine this is a non-licensed (light)version of ModelSim it seems odd that there is a limit on users. Is this ModelSim version supposed to behave like this? Is there a way to avoid this? BR ADSolved3.6KViews0likes7CommentsLinear phase detector implementation for clock and data recovery in FPGA
Hi I am working on a clock-data recovery (CDR) design where the input data stream is 60Mbps (8B10B encoded). Currently I have a working CDR design which uses a binary phase detector (aka. Alexander phase detector) implemented in a Cyclone 10 LP FPGA with an external loop filter and a VCXO. The binary phase detector (BPD) is straight forward to implement in an FPGA, but the a major drawback is the nonlinearity. This makes it very difficult to calculate the loop bandwidth, and jitter peaking can be a problem in cascaded systems. I would prefer to use a linear phase detector, but many of these detectors tends to combine clocks an data signals which is not "FPGA standard", and can be dependent on routing delay. Can anyone recommend (and have experience with) a linear phase detector for CDR which is suitable for FPGA implementation? BR ADSolved1.8KViews0likes2CommentsRe: FIR Filter II, not able to get unity gain
Hi Chee I think I have figured out how to use the FIR II IP to generate a LP filter with: - Unity gain (or close to, will depend on passband ripple) - Max calculation resolution in FIR II - Max dynamic on the output Here is my approach: Generates the filter taps. E.g Matlab. Make sure sum(h(n)) = 1. E.g. taps = 0.0001 0.0006 0.0020 0.0036 0.0028 -0.0040 -0.0173 -0.0288 -0.0212 0.0220 0.1006 0.1897 0.2493 0.2493 0.1897 0.1006 0.0220 -0.0212 -0.0288 -0.0173 -0.0040 0.0028 0.0036 0.0020 0.0006 0.0001 Pre-scaling is the trick. Do not use FIR II auto scale. This will give a non-integer scaling, and unity gain is not achieved. To get max FIR II calculation resolution scale the taps with: 2^M / Max_filter_ripple. Max_filter_ripple is a “compensation factor” needed to avoid overflow for frequencies matching the ripple peaks for the filter, and will typical be slightly above 1. M = Coeffs_resolution-1 + floor(log2(0.5/max(taps))) Max_filter_ripple = 10^(Max_filter_ripple_in_dB/2/20), Max_filter_ripple_in_dB is peak-to_peak. MSBs to remove = ceil(log2(length(taps))) + 1 - floor(log2(0.5/max(taps))) For the filter above, with Coeffs_resolution = 24 M=24, Max_filter_ripple = 1.0058 (with Max_filter_ripple_in_dB=0.1dB) -> At the output: Remove 5 MSB Remove 24 LSB I have tested this approach on a 3-stage decimation filter and I get a gain of 0.98. BR AD1.6KViews0likes1CommentRe: FIR Filter II, not able to get unity gain
Hi Chee, thanks for your reply. My filter is working fine in Matlab. What I am trying to figure out is how to use the FIR II IP correctly: I.e. how to select the 24bit output range from the filter which gives me maximum dynamic without overflow. The DC (zero Hz) gain of the filter equals the sum of the filter taps (SUM(h(n)). If SUM(h(n)) = 1 then filter has gain=1 at DC. This is the case for my filter. In FIR II I have this setup: 24bit input 24bit coefficients Number of coefficients: 26 With these numbers in FIR II the full output range is 53. I assume this is based on: 24 + 24 + ceil(log2(26)) = 24 + 24 + 5 = 53. Is this correct? I notice in FIR II that if one enables the auto-scale the center tap is scaled to 2^23 when using 24bit filter taps. SUM(h(n)) then typical gets larger than 2^24. In my case the sum of the filter coefficients after the FIR II auto scaling is approximately: +29E6 Assuming a range for both + and - values this adds 2 bits. (26bit : +/- 33E6) Based on these numbers the 24bit output range with max resolution without overflow is: MSB to remove: 3 (5-2) LSB to remove: 26 (53-3-24) Is this the correct understanding of the FIR II IP filter? BR AD1.6KViews0likes1CommentFIR Filter II, not able to get unity gain
Hi I have designed a 26 taps FIR filter in Matlab. The coefficients are float (between -1 to 1) and the sum of the coefficient is close to 1 ( sum(taps) = 0.9991 ). In FIR II IP generator (Quartus 17.1) the filter is set up with: - 24b coefficients signed binary with auto scale - 24b input signed binary - 24b output signed binary, where the LSBs are removed to get 24b The problem is that the filter does not have unity gain. Simulations (Matlab and ModelSim) show that the output level is approximately 1/16 of the input level at low frequencies signals (i.e. signals well within the passband). Why? Can anyone share some insight here? Have I configured Fir II incorrectly? I can of course remove some of the MSB bits but I did not think that should be necessary, and one need to be careful to avoid saturation. The FIR filter is part of a 3 stage decimation filter, and if each step has gain loss the dynamic range will suffer. BR AD1.9KViews0likes6CommentsHLS and Time-Division Multiplexing
Hi E.g. when designing a filter using the "FIR II IP Core" you specify both the input sample rate and the clock speed: When the clock rate is far larger than the sample rate the filter generated uses very few DSPs and logic resources. Is it possible to do the same with HLS? Will HLS get Time-Division Multiplexing support? BR ADSolved1.6KViews0likes1Comment