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Re: Read asynchronous sram in 1 cycle
Thanks for your reply. I think I have gotten the key by constraining the timing. I used the ISSI102416 and my system clock is 100MHz. The device has a maxium access time of 10ns. Namely, the data will be available 10ns after it's address is valid. At first, I used two cycles to read data from the sram, the first cycle for output address and the other for get data. This method works of course, but the cost is that the access time is reduced to 20ns. The document "Async RAM Example.doc" helps me a lot. According to the example, I constrains the input delay of sram data signals and finnally achieves my goal. My settings for the sram core are just as follows: Set uptime: 0 cycle. Read wait time: 0 cycle. No read latency. Hope this would help someone else who may meet the same problelm as mine.2.3KViews2likes0CommentsRe: clock mux with internally generated inputs
Originally Posted by Rysc Sorry, but no. I think Altera has one somewhere but not sure. I'm sure there are some on the web somewhere. Might be a good post(maybe a new thread?). Is it a 2:1 mux or larger? The key is to disable one clock(by grounding the output after a falling edge) before enabling the other clock(release it's grouned output after a falling edge). But I just don't have a good piece of code. Hi, have a look to the attached document. I was posted by Kwalt in the year 2008. It is more related to timing analysis, but gives also some hints for clock multiplexing. Kind regards GPK3.6KViews1like0CommentsRe: physical interface between Cyclone III & DAC
Originally Posted by FvM The breakout board that I know (the one documented with the Cyclone III c120 development kit) has a serious disadvantage: It hasn't any ground pins at the debug header. I don't think it's particularly suited to connect single-ended high speed signals. Oh man, that's bogus ... but you are right. Attached is the breakout header schematic that was delivered with the Stratix IV GX development kit. Perhaps the HSMC to GPIO breakout board would be better then. The original poster can download the schematic for that. Thanks Frank! Cheers, Dave8.9KViews1like0CommentsRe: DE2-115 with HSMC_ADA from terasic
By the looks of the photos on the Terasic web site, and the fact that the board can connect via HSMC I/Os or via GPIOs, I'd guess that the signals are single-ended 3.3V or 2.5V LVCMOS. The Terasic HSMC_ADC specification has some pinout details, but its not very explicit, so look at the schematic - I've attached it here. The board uses 3.3V from the host board. The DE115 has jumpers for the HSMC power supply. You'll need to select 3.3V for the bank power. The ADC/DAC use parallel buses at whatever speed you clock the ADC/DAC. The ADC and DAC each have a maximum frequency, but you can clock them at whatever frequency you like below that, eg. clock them both at 50MHz. Cheers, Dave2.4KViews0likes0CommentsRe: Mysterious trouble sharing FPGA RAM with HPS
--- Quote Start --- It looks like a problem with the data cache in the HPS. After writing to the RAM you should flush the data cache, and before reading it you should invalidate it. How are you running your software on the HPS? If it is barebone, there should be some cache management functions with the hardware lib provided by Altera. --- Quote End --- That sounds exactly like my problem - I had read about caches in processor design but it did not occur to me in this case. I'm not running 'bare metal'; I'm running the c-code through the Ubuntu linux that's part of the GHRD. I'm sorry for my ignorance, but some googling revealed several different ways to 'flush the data cache': cacheflush(char *s, int a, int b) as well as other, more platform-specific commands. It also looks like the cacheflush also invalidates the cache, but it's hard to be sure. What command would you suggest or where's a good place to look for more information? Thank you for your quick reply! Have a good weekend Brian1.1KViews0likes0CommentsMAX10 Development Kit Board name, P/N and version corrupt
After successfully having set up Linux on the MAX10 Dev Kit (using the tutorial from rocketboards for rev. C kit) and factory restoring (using the design examples included with the kit), the board name, board P/N, serial number and board version appear to have been corrupted (looking at the Board Test System, see screenshot) - or is this something I should expect? Thanks. https://alteraforum.com/forum/attachment.php?attachmentid=15856&stc=12.3KViews0likes3CommentsRe: Mysterious trouble sharing FPGA RAM with HPS
It looks like a problem with the data cache in the HPS. After writing to the RAM you should flush the data cache, and before reading it you should invalidate it. How are you running your software on the HPS? If it is barebone, there should be some cache management functions with the hardware lib provided by Altera.1.1KViews0likes0Comments