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Altera_Forum
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8 years ago

Mysterious trouble sharing FPGA RAM with HPS

Hello all I'm a hobbyist and I'm trying to learn verilog and FPGA design by building a PDP-8 simulator. I've built the verilog for the PDP8 and it passes all the test code when run on a simulator....
Altera_Forum's avatar
Altera_Forum
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8 years ago

It looks like a problem with the data cache in the HPS. After writing to the RAM you should flush the data cache, and before reading it you should invalidate it. How are you running your software on the HPS? If it is barebone, there should be some cache management functions with the hardware lib provided by Altera.