Msrikanth
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Terasic DE5A-Net DDr board PCIe_DDR4 Ref design regarding
Hi all, I am using the Terasic DE5A-Net-DDR4 board PCIe_DDR4 reference desgin. The refrence design repository is of old Quartus verison. I am curently having Quartus 22.1 and I tried recompiling the design with this Quartus version by IP upgrade. It has compiled but ended up with timing vialations. I did not touched any of the settings. Can any body help me reason for the timing vilations with just re-compilation in the new Quartus verions ? Thanks in Advance Srikanth452Views0likes1CommentIntel Clock crossing bridge IP core simulation Reg
Hi all, I am working on a design with two clock domains (PCI express clock) and RTL with different clocks. For this I have used Intel Clock crossing bridge IP core in the platform Designer. It has resolved the timing issues but the design is not working. I tried simulating the design with the pre-compiled libraries of the CCB in Model-sim and its not giving any output. Can anybody guide where can I get the simulation files for the clock crossing bridge.630Views0likes1CommentCompilation time of Quartus Prime Pro
Hi all, currently Iam working on Quartus Prime Pro 22.1 version with multi core Workstation with 128 GB RAM. But for a reasonably complex design with Platform Designer IPs is taking too much time more than 1 hour. And the tool is not utilising all the CPU cores. Can anybody suggest me to improve the compilation time of the tool please.557Views0likes2CommentsALTPLL MegaWizard Plugin GUI not responding
Hi all, I am using Quartus 15.1 on Linux environment with 64 GB RAM based HP workstation. When I am trying to create and add a ALTPLL IP megafunction, its not going ahead and some times misbehaving and ultimately hanging. Has anybody encountered same issue? Any solution ? Thanks in Advance Srikanth1.1KViews0likes1CommentIs ALTGX IP is necessary for 160 Mbps stream driving?
Dear all, I am working on Terasic TR-4 230K development kit with XTS Daughter Card with one of the HSMC connector. I want to generate some random serial data and transmit through the SMA connector of XST daughter card at 160 Mbps rate and analyze on Scope. My queries are Do i need to instantiate ALTGX ip for my data rates of 160 Mbps? If so, what should be the data width of ALTGX in datain and out? Thanks & Regards Srikanth1.4KViews0likes1Comment