Intel Clock crossing bridge IP core simulation Reg

Hi all,

I am working on a design with two clock domains (PCI express clock) and RTL with different clocks. For this I have used Intel Clock crossing bridge IP core in the platform Designer. It has resolved the timing issues but the design is not working. I tried simulating the design with the pre-compiled libraries of the CCB in Model-sim and its not giving any output. Can anybody guide where can I get the simulation files for the clock crossing bridge.