JPott5
New ContributorJoined 6 years ago
User Profile
New Contributor
User Widgets
Contributions
Building minimal Simple Socket Server on MAX10
Can the TSE IP block configured for 100/10MB run from OnChip Ram only? Do I have to include MSGDMA interfaces? Is there a document explaining how to configure platform designer to produce the hw layer for the Simple Socket Server template? I can only find example code which when I modify it either wont build or builds and wont run or crashes when it runs. I cant find documentation that explains what are the expected minimum Platform Designer requirements for making the Simple Socket Server project template in Nios II software build tool work. I am using Quartus prime lite V18.1 but could switch to a newer version if needed. I have a MAX1000 board to which I have connected a DP83848 evaluation board.1.2KViews0likes2CommentsRe: Can you help me find examples of use of Basic IP for such as the FIFO IP block for use with Max 10?
Anand thans for your reply and the useful links included, I am up and running now. I would add that watching the "How to begin a Simple FPGA Design" video on YouTube is a very good starter showing how to create a project with Block schematic, creating schematic symbols from your HDL code and use of IP.821Views0likes0CommentsCan you help me find examples of use of Basic IP for such as the FIFO IP block for use with Max 10?
I have found the user guide but it doesn't explain how to integrate the generated IP into my existing verilog code. Is there examples of a RAM type IP integrated into a simple LED/ push button project? (Ideally for the MAX 10946Views0likes3CommentsWhat is the simplest way to implement a memory interface on the MAX 10?
My FPGA design reads serial data from a number of serial interfaces, packages it up and needs to make it available to a separate micro controller via an 8 bit parallel bus. What is the best way to do this?667Views0likes1CommentRe: How do I get started?
Hi Vicky, It looks like there was a problem with my USB Blaster, I have got hold of another one and it just works! Thanks for your help and patience. Now I just need to work out how to define and use some LVDS inputs and outputs on the Max10 (any suggestions would be appreciated) and I will be away. Thanks again John1.9KViews0likes0CommentsRe: How do I get started?
Vicky, I am also struggling to work out what support is available to me, for example when I try to access training courses such as The Quartus Software Interactive Tutorial I either get : Resource at '/content/altera-www/global/en_us/index/support/training/course/odsw1050.html' not found: No resource found RequestURI=/content/altera-www/global/en_us/index/support/training/course/odsw1050.html Servlet= /apps/sling/servlet/errorhandler/404.jsp ApacheSling/2.4 (jetty/9.2.17.v20160517, Java HotSpot(TM) 64-Bit Server VM 1.8.0_162, Linux 4.4.21-69-default amd64) OR The I get the attached response when I attempt to register for a course. Its really blocking ability to move forward with evaluating the Max 10 for a new project.1.9KViews0likes3CommentsRe: How do I get started?
Hi, Under the Currently selected hardware drop down menu USB-Blaster is not shown. unfortunately I cant take a screenshot showing that drop down open. Attached you will find the screenshot of Device manager showing the USB-Blaster entry. I have also gone through the troubleshooting suggestions in the, 'ug_usb_blstr Intel FPGA download cable user guide.pdf' document. Here is the response to the jtagconfig --serverinfo command: C:\altera\16.0\quartus\bin64>jtagconfig --serverinfo Installed JTAG server is 'C:\altera\16.0\quartus\bin64\jtagserver.exe' Service manager reports server is running Server reports path: C:\altera\16.0\quartus\bin64\jtagserver.exe Server reports version: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition Remote clients are disabled (no password) C:\altera\16.0\quartus\bin64>jtagconfig No JTAG hardware available Regards John1.9KViews0likes0Comments