New ContributorMy FPGA design reads serial data from a number of serial interfaces, packages it up and needs to make it available to a separate micro controller via an 8 bit parallel bus. What is the best way to do this?
Frequent ContributorHello Sir,
Do you mean memory interface like DDR3, DDR2? If yes, you may refer to the EMIF User guide to the implementation.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_emi.pdf
By the way, if the require memory density is not much, then you can consider the on-chip memory.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf
