ContributionsMost RecentMost LikesSolutionsRe: EM2130L Regulator with external Sync clock Can the "alteraforum.com" link be updated now that this is Intel? Is there any additional information regarding the SYNC pin? Specifically, can an 800kHz spread spectrum clock be used to drive SYNC? Re: EM2130L Regulator with external Sync clock Can the "alteraforum.com" link be fixed now that this is Intel? Is there any additional information about the SYNC input pin? Specifically, can an 800kHz spread spectrum clock be used as input? Re: Quartus DSE Fatal Error All 4 of the computers (3 that work and 1 that fails) have the same operating system = Windows 10. This is supported for Quartus 19 per the link you sent. All 4 computers were recently re-imaged and thus have received the same OS, updates, and tool installs. Additionally, they all are operating on the same source that comes out of source control. I am curious about the stack trace that I provided. Does that give any clues as to specifically what the hang-up could be? As I mentioned earlier, I am able to complete synthesis and implementation if I use the Quartus GUI and it also works if I tell DSE to only build 1 instance at a time. Ironically, the failing computer has the most RAM and the most computing horsepower out of all 4 computers. Re: Quartus DSE Fatal Error I am not sure that I can provide sample project yet (due to IP) and I am not sure that it would necessarily be helpful because you probably wouldn't be able to reproduce the error. I setup 3 more computers to run DSE with the exact same version Quartus and exact same source. These other three computers didn't have any problems running 3 simultaneously. One of those has only 32GB of RAM and two less CPUs. Thus, it is probable that you wouldn't see the failure because it is not due to the source specifically. Each time it fails, the stack trace below is given in the DSE window. Does this give any clues as to what is happening? ============================================================================== Error: Exploration Point a_1 reported: *** Fatal Error: Access Violation at 0X00007FFD47EFA2C4 Module: quartus_map.exe Stack Trace: 0x1a2c3: HDB_INSTANCE_NAME::keep_obsv_name + 0x63 (DB_HDB) 0x15095: HDB_SYN_INSTANCE_NAME::keep_obsv_name + 0xd (DB_HDB) 0x41360: HDB_NAME_MGR::keep_obsv_name + 0x2c0 (DB_HDB) 0x3857e: SGN_UTILITY::garbage_collect_names_before_synthesis + 0x2ee (synth_sgn) 0xc72ec: SGN_EXTRACTOR::synthesis_and_post_processing + 0xbc (synth_sgn) 0x13493: sgn_qic_helper + 0x173 (synth_sgn) 0x44d3: qsyn_execute_sgn + 0x263 (quartus_map) 0x14246: QSYN_FRAMEWORK::execute_core + 0x136 (quartus_map) 0x13b9f: QSYN_FRAMEWORK::execute + 0x30f (quartus_map) 0x112a9: qexe_do_grunt + 0xb9 (comp_qexe) 0x16546: qexe_run + 0x356 (comp_qexe) 0x17371: qexe_standard_main + 0xc1 (comp_qexe) 0x1b42b: qsyn_main + 0x53b (quartus_map) 0x133a8: msg_main_thread + 0x18 (CCL_MSG) 0x14bae: msg_thread_wrapper + 0x6e (CCL_MSG) 0x16af0: mem_thread_wrapper + 0x70 (ccl_mem) 0x12c41: msg_exe_main + 0xa1 (CCL_MSG) 0x2a236: __tmainCRTStartup + 0x10e (quartus_map) 0x17033: BaseThreadInitThunk + 0x13 (KERNEL32) 0x526a0: RtlUserThreadStart + 0x20 (ntdll) End-trace Re: Quartus DSE Fatal Error I think 64GB should easily be enough for 3 simultaneous compilations based upon past experience. I did, however, change to 2 as another experiment and got the same result. Then, I changed the virtual memory to be 4x the RAM size. Still failed in exactly the same way. Quartus DSE Fatal Error I am trying to run Quartus Design Space Explorer with 3 parallel compilations. After about 20 minutes (at quartus_map stage), two of the compilations will error out with "Fatal Error: Access Violation" message. I have successfully run DSE many times before so I am familiar with how to use it. This particular DSE instance is running on a new computer for which I just installed the tools fresh. I am using Quartus 19.1.0 Build 670 09/22/2019 SJ Standard Edition. Patch 0.02std has been installed as has WSL (Windows Subsystem for Linux). A single instance of the design completes compilation using the GUI and one (and only one) of the compilations from a parallel set in DSE has completed successfully also. Sometimes all of the compilations will fail. The computer has plenty of hard disk space. The CPU is i7-8700K @ 3.70GHz. There is 64GB of RAM. The DSE setup allows for all processors to be used for the 3 compilations. The computer is not running anything else. What could be causing this issue? Re: parameter passing for IP in Platform Designer (Qsys) The device is Stratix V and the bar space interface is memory mapped. I don't think these matter. I contacted local FAE about the issue. They are checking on whether it is possible to pass parameters into an instantiated QSys system. Our prior workaround has been to post-process the synthesized verilog file that is created after QSys generation step. The post-processing adds code for the parameters. FAE is checking to see if there is a more elegant way than post-processing with script. parameter passing for IP in Platform Designer (Qsys) I have a design which was originally done in Quartus 15.1. We passed some parameters into QSys (now Platform Designer) for configuration of the altera_pcie_256_hip_avmm IP. I have recently moved the design forward to version 19 but get errors that seem to imply that I either can’t pass parameters into QSys anymore or that maybe the parameter name changed. The original code had the PCIe_DEVID defined as a parameter in a wrapper verilog file. Later on in the same verilog file, there is a defparam followed by the instantiation of the qsys system. This worked for Quartus 15 but does not work for Quartus 19 defparam u0.PCIE_DEVID=PCIE_DEVID mySystem_qsys u0 ( // port connections ) Inside the qsys system is the altera_pcie_256_hip_avmm IP which has the field for the PCI device ID that I am trying to set. The error I receive is: "12077 Node instance "u0" instantiated with unknown parameter "PCIE_DEVID". Its almost as if either the name of the parameter field changed in the IP block or maybe defparam has been deprecated. I tried using Instance Parameters for passing into the qsys system that was unsuccessful. Can you help me with the proper syntax to accomplish what used to work with Quartus 15? Thanks. Re: Does Platform Designer work on Ubuntu 18.04? I have this exact same problem: Ubuntu 18.04LTS and Quartus 19.1. I have installed the prerequisites per the installation document located at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/archives/quartus_install-19-1.pdf . Qsys fails with this message on a simple PIO: Can't locate Getopt/Long.pm in @INC (you may need to install the Getopt::Long module) (@INC contains: /opt/Intel/QuartusPrimeStandard_19.1/quartus/sopc_builder/bin/europa /opt/Intel/QuartusPrimeStandard_19.1/quartus/sopc_builder/bin /opt/Intel/QuartusPrimeStandard_19.1/quartus/../ip/altera/sopc_builder_ip/common /opt/Intel/QuartusPrimeStandard_19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio /tools/perl/5.28.1/linux64/lib/site_perl/5.28.1/x86_64-linux /tools/perl/5.28.1/linux64/lib/site_perl/5.28.1 /tools/perl/5.28.1/linux64/lib/5.28.1/x86_64-linux /tools/perl/5.28.1/linux64/lib/5.28.1) at /opt/Intel/QuartusPrimeStandard_19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl line 18. This design didn't have any problem with version 18.1. Re: I have a DSPBA block that is functionally working but the timing in the overall system needs to be improved. DSPBA is giving me an error that doesn't make sense.Hi YY. Attached is the detailed info. I don’t want this posted to the forum per my company’s policy. Myron