BAdam1
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PS configuration with processor
We are using the PS method to program a Cyclone 10 GX FPGA with the SPI interface of a processor. We are changing the FPGA to a larger device. Is there a command to determine the device type using the PS configuration method? We need to determine the device so that the correct rbf image gets loaded.615Views0likes1CommentUART core simulation
I am using Quartus Lite 20.1.1 to simulate the UART core. I am using Nativelink to run the simulation. There is an issue with the baud divisor in simulation. If you select FIXED BAUDRATE in Platform Designer, the simulation accepts the write to the divisor. If the box is left unchecked, it always loads the baud divisor from divisor_constant in the simulation code. I have verified the baud divisor and send data at the correct baud rate to the rxd pin. The RRDY bit never gets set. The status register always reads 0x60 with TRDY and TMT set.798Views0likes1CommentRe: Does the Intel FPGA Avalon I2C (Master) Core issue a STOP after receiving a NACK? If not, how can just a STOP be issued without transmitiing any data.
If the I2C Master Core gets a NACK when the device address is transmitted, how does it behave? Does it just set the MAK bit in the ISR? Does it issue a STOP? Does the driver need to issue the STOP or a repeated START?1.2KViews0likes0CommentsRe: The Knowledge Base shows that Vcc (0.9V), and Vccp (1.8V) should come up before Vcceram (0.9V), Vccr_gxb (1.8V), and Vcct_gxb (0.95V). This requires splitting the voltages and adding power switches to sequence the voltages. Is this required?
This is for a Cyclone 10 GX device. The device part number is 10CX085YU484I5G.1.1KViews0likes0CommentsThe Knowledge Base shows that Vcc (0.9V), and Vccp (1.8V) should come up before Vcceram (0.9V), Vccr_gxb (1.8V), and Vcct_gxb (0.95V). This requires splitting the voltages and adding power switches to sequence the voltages. Is this required?
What are the ramifications of not sequencing these power rails? Does it cause configuration issues, functional problems, or long term reliability issues?1.3KViews0likes3CommentsRe: Do VCCIO 1A and VCCIO 1B need to be at 2.5V when using ADC in 10M16DA U324?
Page 14 refers to a Single Supply MAX10 device. I am using a dual supply MAX10 device. 10M16DA U324 Page 23 shows a Dual supply implementation with the ADC. The question remains can VCCIO1A and VCCIO1B be tied to 3.3V when using the ADC in a dual supply device. All examples show 2.5V.574Views0likes0CommentsDo VCCIO 1A and VCCIO 1B need to be at 2.5V when using ADC in 10M16DA U324?
Let fitter pick pins and Quartus assigned 3.3V pins to VCCIO 1A and VCCIO 1B with ADC instantiated in design. PCG is not very clear about the voltage for these banks when using the ADC in a dual supply device.886Views0likes2CommentsNativelink fails simulating altera_gpio_lite for MAX10 in Quartus 18.1.1 Lite
# vlog -vlog01compat -work work +incdir+C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA {C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA/GPIO_bi.vo} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:16:55 on Aug 09,2019 # vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA" C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA/GPIO_bi.vo # ** Error: (vlog-7) Failed to open design unit file "C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA/GPIO_bi.vo" in read mode. # No such file or directory. (errno = ENOENT) # End time: 11:16:55 on Aug 09,2019, Elapsed time: 0:00:00 # Errors: 1, Warnings: 01KViews0likes1Comment