eolse
New ContributorJoined 7 years ago
User Profile
New Contributor
User Widgets
Contributions
Re: Stratix 10 DX Production board is missing ALL examples design files
The solution to my own problem is: Use Quartus Version 19.4 to download .sof files to the Stratix 10 DX board, NOT Quartus version 19.3 which is indicated by the board design file examples. It appears the Quartus Version 19.4 has the ".01" patch that fixes the programmer, so now the Quartus programmer can be trained to recognize the correct JTAG device chain. The user must auto detect the chain first. Then select a generic Stratix 10 DX part that most closely matches the development board part. IN my case, it will be the 1SD280PT2. Then, press "add file" using the desired .sof file. Another device will appear, which is the device contained within the .sof file. Then delete the generic 1SD280PT2 part and make sure the correct .sof placed part (i.e., 1SD280PT2F55) is in the place of the generic part you indicated before. This is best way to accommodate any changes to the part details you may be supporting. The .sof file should download. This procedure was tested so far with Ver 19.3, Version 19.4, and Version 21.4. Only Version 19.4 works of these three tested. In my case, using Version 19.4, the critical VID settings were defaulted to a state that works. Here are the VID settings that work with my Stratix 10 DX PRODUCTION development board:Stratix 10 DX Production board is missing ALL examples design files
The Stratix 10 DX PRODUCTION development board is missing ALL the example files. This is making it very difficult to use the board test program. There are many conflicts, from the device files, to the Quartus version, to the Empirion VID settings, etc. I cannot download a single SOF file to the board, as it complains aboout my PMBus address settings. Does anybody know what I'm doing wrong? Here's the error: Info(16677): Loading synthesized database. Info(16678): Successfully loaded synthesized database: elapsed time is 00:00:00. Info(16677): Loading final database. Info(16678): Successfully loaded final database: elapsed time is 00:00:00. Info(19848): Regular SEU info => 105 sector(s), 8 thread(s), 31500 interval time in microsecond(s) Info(19848): IO hash is BB750EB97D4B609970D98035AA815B7E2BD7D5F68F14829805A8E595293B9B19 Info(19848): Keyed hash is 24475034D7B2293984104136B524F8B810370248669C06141D350D29760E96F1 Info(19848): Design hash is 603524EF607B41F47C89B1D3C941A195F33E399B73DF8359B05F0ECE5E812208 Info(19848): IO hash is BB750EB97D4B609970D98035AA815B7E2BD7D5F68F14829805A8E595293B9B19 Info(19848): Keyed hash is 9B2E2027B3461CC6203BBA88832337376CAAA6E5A8CA3583A64791119B55DAF9 Info(19848): Regular SEU info => 105 sector(s), 8 thread(s), 31500 interval time in microsecond(s) Info(19848): IO hash is BB750EB97D4B609970D98035AA815B7E2BD7D5F68F14829805A8E595293B9B19 Info(19848): Keyed hash is 24475034D7B2293984104136B524F8B810370248669C06141D350D29760E96F1 Info(19848): Design hash is 603524EF607B41F47C89B1D3C941A195F33E399B73DF8359B05F0ECE5E812208 Info(19848): IO hash is BB750EB97D4B609970D98035AA815B7E2BD7D5F68F14829805A8E595293B9B19 Info(19848): Keyed hash is 9B2E2027B3461CC6203BBA88832337376CAAA6E5A8CA3583A64791119B55DAF9 Info(16677): Loading final database. Info(16734): Loading "final" snapshot for partition "root_partition". Info(16734): Loading "final" snapshot for partition "auto_fab_0". Info(16678): Successfully loaded final database: elapsed time is 00:00:01. Info(209060): Started Programmer operation at Sun Apr 10 10:02:46 2022 Info(18942): Configuring device index 2 Error(18950): Device has stopped receiving configuration data Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00200008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Intel Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Error(209012): Operation failed Info(209061): Ended Programmer operation at Sun Apr 10 10:02:55 2022 I've tried so many combinations of VID setting, and recompiled the examples under several different versions of Quartus, but keep getting this error! I find this un-acceptable for a development board that is costing this much.Re: Stratix 10 FPGA programming not happening in Intel® Stratix® 10 DX FPGA Development Kit
I am having a similar issue. I can't program the Stratix DX development board. It fails at about 6%. I've updated the power management and VID according to the notes for supporting the emperion power management chips. It looks like my PMBus addresses are wrong. Here is the message: Error(18950): Device has stopped receiving configuration data Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00200008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Intel Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Error(209012): Operation failed Can anybody help me with programming this device Please!Re: Does Quartus PRO supports 'HDL convert to bsf file' function？
Yes, thanks for the tip. What I'm doing is keeping a dummy project open in the Standard edition, and that allows me to generate .bsf symbols for my project in the Pro edition. I just load the files I need to create in standard, and update them from Pro. I keep two File Explorer windows open so I can slide some of the .bsf symbol files created in Standard edition over to the correct directory. There is great misunderstanding by Intel when it comes to schematic level/block level design entry for FPGAs. Intel must be thinking we're using "AND" gate symbols or something like that out of their old library. That's not what we're doing! What engineers are doing is building complex modules in Verilog or VHDL. Once that's debugged, they convert the module to a block diagram, just like the Intel IP does now. The reason Engineers do this, is because the complexity of the module interconnections is made simple. For example, consider a systolic matrix multiplier comprised of many sub-module ALU units. It's just easier to connect these ALU modules into a full-blown matrix multiplier using the block symbol approach. Once that is done, we convert the top-level schematic back to Verilog for simulation. Block diagrams that are generated automatically from your Verilog code is NO replacement for the block diagram structure created by the designer. This is another misconception. I DO see why Intel doesn't want to support the old .bsf symbol creation process in Pro. But just taking it out is the wrong action. Intel should create a way to create .bsf files from the IP configurator platform and allow engineers to drop associated .sdc files to be associated with those symbols. In other words, Intel CAN make the .bsf symbol generation compliant to their new directory structure under Pro. Apparently, Intel doesn't want to. If Intel was thinking of electrical engineers, and how EE's might pollenate new applications for Intel devices, then Intel should provide an easy method to encrypt our Verilog during the symbol creation process. (IEEE standard made easy). (It's another problem Intel doesn't understand .... Electrical Engineers end up going into the software profession because software can easily be developed and licensed. On the other hand, electrical engineers are being stripped of any such opportunities (and I hate to say it .... by Intel). Lastly, Xilinx Vivado supports block diagrams throughout the entire design process. There is no limiting the Engineers ability to use block symbols. But if Quartus can solve this simple issue, make the schematic capture software a bit better, then Intel would really have a leg up over Xilinx. It's a shame. So, until Intel realizes that this decision was very poorly made, I'll need to work between the standard and Pro editions to get the job done! Ooouch!!! Look, some of these feature deprecations are being decided because of other factors, like not having control over the schematic software. Fix that! Regards, Eric OlsenRe: Does Quartus PRO supports 'HDL convert to bsf file' function？
Kenny, I don't want to be-labor this point ... but the idea that Intel wants to move Engineers back to HDL coding is ridiculous. Intel is telling us they want to move us to a higher level of abstraction. That's all that the schematic does .... is gives us a higher level of abstraction! SCHEMATICS ARE IMMEDIATELY CONVERTED TO HDL BEFORE COMPILING NOW! if Intel would put a little more effort into the schematic editor, the symbol editor, and make it part of platform designer, that would be a big help for us, and for Intel. Some point's Intel should consider: 1) SCHEMATICS ARE IMMEDIATELY CONVERTED TO HDL BEFORE COMPILING NOW ANYWAYS! 2) QUARTUS PRO ALREADY SUPPORTS BLOCK SYMBOLS FOR ALL ITS IP !!!!!!!!!!!!!!!!!!!!!! (you can't claim what you're claiming) REMEMBER .... XILINX VIVADO still supports block symbol entry with total backing !!!! This whole deprecation (converting HDL to .BSF) is stopping engineers from developing their own IP !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -CheersRe: Does Quartus PRO supports 'HDL convert to bsf file' function？
Kenny, Please let your Quartus Pro software designers know that the solution to this problem is very simple. All that is needed is to incorporate the .BSF symbol building function as part of the Platform or IP Designer programs. By simply providing an option to build a .bsf instead of a full IP module from the library, this allows the .bsf symbol to be treated exactly like the .IP files, and everything works perfectly! Even things like .SDC constraint files and IEEE encryption can be managed using this .bsf symbol approach. That should would help us old poor electrical engineers out here with no way to manage our own IP! (P.S., I'm not such a beginner!) -CheersRe: Does Quartus PRO supports 'HDL convert to bsf file' function？
Deprecating the ability to convert HDL to .bsf format should not affect the integrity Intel's platform design, and this is a huge mistake. It is now nearly impossible for me to port a previous design in Quartus Standard edition to Quartus Pro edition because of this deprecation. The designers of Quartus should know that symbol files are converted to specific instances of the Verilog module, and so there is no portability if we cannot regenerate the block symbols in the Pro version. So it's a huge mess with no apparent work-around other than try to go back to standard edition.Re: encrypt my IP
I designed a co-processor to the NIOS, its taken five years, but I cannot sell it due to the fact that Quartus has no portal or capability to protect my IP. Only Intel themselves, and their very select partners, get to have the benefit of IP protection. I hoipe Intel someday realizes this is a major flaw in their policy. This is why hardware engineers cannot get anywhere in today's markets. Software is protected for start-ups, hardware IP in FPGA's is NOT.
