ContributionsMost RecentMost LikesSolutionsHAL Kernel Version Mismatch Error During FPGA Emulation with vector-add Sample Hello Intel FPGA team, I'm currently working on the vector-add example from the official oneAPI-samples repository, specifically from: DirectProgramming/DPC++/DenseLinearAlgebra/vector-add I’m encountering the following runtime error when I attempt to run the emulation build: Error output: ./vector-add-buffers.fpga_emu HAL Kern: Version mismatch! Expected 0xa0c00001 but read 0x4130 Hardware version ID differs from version expected by software. Either: a) Ensure your compiled design was generated by the same ACL build currently in use, OR b) The host can not communicate with the compiled kernel. vector-add-buffers.fpga_emu: /nfs/sc/disks/swip_hld_1/ops/SC/hld/nightly/2022.1/96.2/l64/work/acl/acl/source/57c9d2bcb46afcf445b5da2406c0e6d85be93ef3/src/acl_kernel_if.cpp:733: int acl_kernel_if_init(acl_kernel_if*, acl_bsp_io, acl_system_def_t*): Assertion `0' failed. make: *** [Makefile.fpga:35: run_emu] Error 1 Environment details: Board: DE10-Agilex BSP Path: /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/board/de10_agilex oneAPI version: Installed multiple versions. Active: 2022.0.2 dpcpp path: /opt/intel/oneapi/compiler/2022.0.2/linux/bin/dpcpp OS: Ubuntu (detected as Rocky Linux during install attempts) What I have tried: Verified the AOCL_BOARD_PACKAGE_ROOT is correctly set. Recompiled the design using make clean && make fpga_emu. Ran aoc -list-board-packages to confirm the installed board. Ensured Quartus, BSP, and compiler are aligned. Despite that, I still encounter the HAL version mismatch. Request: Could someone guide me on how to: Resolve this version mismatch issue? Confirm the correct environment and runtime versions are in sync? Completely clean older/duplicate oneAPI installations if that’s the root cause? @intel @OneAPI @fpga @agilex7 @de10 @intel6 Re: LLM Implementation on DE10-Agilex Board Hi, Yes, currently I'm planning to use Altera FPGA AI Suite and later on i'll use own LLM algorithm. Would you help me in getting the resources or guidance to implement LLM using this Altera FPGA AI Suite. LLM Implementation on DE10-Agilex Board I am currently working on implementing a large language model (LLM) and am exploring the feasibility of deploying it on the DE10-Agilex development board, which features the Intel Agilex FPGA (AGFB014R24B2E2V). Could you please confirm whether this board supports such implementations? Additionally, I would appreciate any guidance on the required configuration or recommended setup for enabling LLM inference on this platform. @agilex7 @Agilex @llm