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BobA

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Re: Trouble licensing Questa Starter Edition
I removed the MGLS_LICENSE_FILE environment variable, but I'm still getting the "Unable to checkout a license" error.
7 months ago Place Quartus® Prime
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Re: Trouble licensing Questa Starter Edition
I have of course, several network interfaces and several MAC addresses. But my active ethernet connection's MAC address matches the one in the license file. lmutil says "This is the correct node for this node-locked license". Doesn't that mean the MAC addresses match? - Bob
7 months ago Place Quartus® Prime
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Re: Trouble licensing Questa Starter Edition
You mean because of the forward slashes? OK. I changed them to backslashes, re-started Quartus, and tried running the RTL simulator. I still got the Fatal License Error.
7 months ago Place Quartus® Prime
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Re: Trouble licensing Questa Starter Edition
Thank you. I added MGLS_LICENSE_FILE. Here's my environment: I still get the Fatal License Error when starting RTL Simulation: Here's what I see when I run lmutil lmdiag: C:\altera\13.0sp1\quartus\bin>lmutil lmdiag lmutil - Copyright (c) 1989-2008 Acresso Software Inc. All Rights Reserved. FLEXnet diagnostics on Tue 7/15/2025 09:19 ----------------------------------------------------- License file: C:\Users\Bob\AppData\Roaming\LR-240159_License.dat ----------------------------------------------------- "intelqsimstarter" v2026.06, vendor: mgcld uncounted nodelocked license, locked to ethernet address "10ffe03bda88" starts: 27-jun-2025, expires: 27-jun-2026 This is the correct node for this node-locked license ----------------------------------------------------- C:\altera\13.0sp1\quartus\bin>
7 months ago Place Quartus® Prime
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Trouble licensing Questa Starter Edition
Hi, I have Quartus Prime Lite 24.1std.0. I select Tools->Run Simulation Tool->RTL Simulation and get a Fatal License Error, Unable to checkout a license. I've gotten a license file from Intel and set LM_LICENSE_FILE to point to it. When I run lmutil lmdiag, I get: lmutil - Copyright (c) 1989-2022 Flexera. All Rights Reserved. FlexNet diagnostics on Fri 6/27/2025 12:15 ----------------------------------------------------- License file: C:\Users\Bob\AppData\Roaming\LR-240159_License.dat ----------------------------------------------------- "intelqsimstarter" v2026.06, vendor: mgcld, expiry: 27-jun-2026 vendor_string: D59A5B02 uncounted nodelocked license, locked to ethernet address "10ffe03bda88" starts: 27-jun-2025, expires: 27-jun-2026 This is the correct node for this node-locked license ----------------------------------------------------- In Quartus' Options dialog, under EDA Tool Options, the Questa Intel FPGA is set to c:/intelfpga_lite/24.1std/questa_fse/win64. There is a Questasim installation there. What could be going wrong? Thank you.
8 months ago Place Quartus® Prime
Simulation
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Re: Trying to understand on-chip memory
Do you have further inquiries regarding this case? No, I think I get it. Thanks.
8 months ago Place Quartus® Prime
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Trying to understand on-chip memory
Hi. I'm using the ROM: 1-PORT in the IP Catalog. I've been unable to find a code example of accessing that on-chip memory. I hope someone here can help. The IP Catalog wizard generates code for a module: module rom ( address, clock, q); input [10:0] address; input clock; output [7:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [7:0] sub_wire0; wire [7:0] q = sub_wire0[7:0]; altsyncram altsyncram_component ( .address_a (address), .clock0 (clock), .q_a (sub_wire0), .aclr0 (1'b0), .aclr1 (1'b0), .address_b (1'b1), .addressstall_a (1'b0), .addressstall_b (1'b0), .byteena_a (1'b1), .byteena_b (1'b1), .clock1 (1'b1), .clocken0 (1'b1), .clocken1 (1'b1), .clocken2 (1'b1), .clocken3 (1'b1), .data_a ({8{1'b1}}), .data_b (1'b1), .eccstatus (), .q_b (), .rden_a (1'b1), .rden_b (1'b1), .wren_a (1'b0), .wren_b (1'b0)); defparam altsyncram_component.address_aclr_a = "NONE", altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS", `ifdef NO_PLI altsyncram_component.init_file = "G:/My Drive/microcode1.rif" `else altsyncram_component.init_file = "G:/My Drive/microcode1.hex" `endif , altsyncram_component.intended_device_family = "MAX 10", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 2048, altsyncram_component.operation_mode = "ROM", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_reg_a = "CLOCK0", altsyncram_component.widthad_a = 11, altsyncram_component.width_a = 8, altsyncram_component.width_byteena_a = 1; endmodule and then I instantiate in my own Verilog code: rom rom_inst (.address ( address ), .clock ( clock ), .q ( q )); What I don't understand is what q should be. Should it be 'reg [7:0] q;' or 'wire [7:0] q;'? It seems to me, it would have to be a reg, especially since we're using a clock to fetch memory. But look at lines 12-18 in the generated module: 12 wire [7:0] sub_wire0; 13 wire [7:0] q = sub_wire0[7:0]; 14 15 altsyncram altsyncram_component ( 16 .address_a (address), 17 .clock0 (clock), 18 .q_a (sub_wire0), It's using a wire to receive the memory contents! I would've thought that, inside altsyncram, there's an always block that, on the rising edge of clock0, reads the memory contents into a register. But a wire makes me think it's just combinational. And what does that mean for my code? Do I need an always block clocking the rom module's q output into a register? And when should I do that? I assume I cannot trust that q has valid data on it, at the same clock rising edge that triggered the memory read. I need to wait for the memory access time, right? Thank you for your help.
Solved
8 months ago Place Quartus® Prime
Hdl
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Re: How to fix "Warning (10030): Net "microcode1.data_a" at MAX10CPU.sv(10) has no driver or initial val
Yes, sstrell's suggestion helped.
9 months ago Place Quartus® Prime
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Re: How to fix "Warning (10030): Net "microcode1.data_a" at MAX10CPU.sv(10) has no driver or initial val
It's just the extension. I know the file's contents are in $readmemh's format. The bigger concern is that the 'initial' block doesn't get synthesized. But is there another way to initialize memory in the synthesized Verilog?
9 months ago Place Quartus® Prime
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Re: How to fix "Warning (10030): Net "microcode1.data_a" at MAX10CPU.sv(10) has no driver or initial val
If there's another way to do this, I love to hear about it. I didn't really understand your previous comment about using a .dat file. The .mem file I'm using is in the format accepted by $readmemh.
9 months ago Place Quartus® Prime
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