Trying to understand on-chip memory

You should declare the output q as a wire, because the ROM module already registers the output internally.

You do not need to add your own always @(posedge clk) just to capture q, unless you want to add pipeline stages or synchronize it further.

The altsyncram component is configured with:

altsyncram_component.outdata_reg_a = "CLOCK0"

This means the output is registered on the rising edge of clock0 inside the IP — so the ROM fetches data synchronously, with output changes one clock cycle after the address is applied.

So even though q is declared as a wire, it is driven by a register inside the ROM IP. That’s why your code can simply declare:

wire [7:0] q;
rom rom_inst (
 .address (address),
 .clock (clock),
 .q  (q)
);

And it should works exactly as a synchronous ROM should.

So yes — you're absolutely right: you cannot use q on the same clock edge that you apply the address. You need to wait one clock cycle.

Regards,

Richard Tan