NoahHuguenin
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Re: Assertion failed in "hdl.cpp" when compiling HLS design
Hello again, and thank you very much for your suggestions! I would have had a hard time figuring this out otherwise. I think the information provided here should be enough for me to correct my design in the coming days. Regards and best wishes, Noah1.6KViews0likes0CommentsRe: Assertion failed in "hdl.cpp" when compiling HLS design
Hello @Jessica_Intel @BoonBengT_Altera , Thank you for your answers! Excuse me for not clarifying, cfixed_t is defined in my .h file as: typedef struct complex_fixed { fixed16 real; fixed16 imag; } cfixed_t; And fixed16 is defined as typedef ac_fixed<16, 3, true,AC_RND, AC_WRAP> fixed16; The only C++ non-HLS libraries I use are stdio.h and ctime.h, but I have used them in other projects with no problems. That is why I suspected the mm_host as the cause of the error, since I had not used this type in previous tests. In any case, here is a somewhat simplified version of the test, with which you should be able to replicate this error. The build command is included in a .txt file within the project folder. Regards, Noah1.8KViews0likes0CommentsAssertion failed in "hdl.cpp" when compiling HLS design
Good day! I'm working with Quartus Prime Pro 24.2 and its corresponding version of HLS Compiler. I get the following error message shortly after launching compilation, with an Agilex 7 board as target: Assertion failed: size >= 1, file hdl.cpp, line 201 HLS System Integration FAILED. It seems like this hdl.cpp file is nowhere to be found in my disk. I cannot share the design as it is, since it includes a confidential module, but it might be relevant is that the error appears since I started testing it with mm_host interfaces. In case it might be relevant, here are the interface types I am using: typedef ihc::mm_host<cfixed_t, ihc::dwidth<1024>, ihc::awidth<10>, ihc::latency<0>, ihc::waitrequest<true>, ihc::aspace<1>> mm_host_t1; typedef ihc::mm_host<cfixed_t, ihc::dwidth<1024>, ihc::awidth<2>, ihc::latency<0>, ihc::waitrequest<true>, ihc::aspace<2>> mm_host_t2; typedef ihc::mm_host<cfixed_t, ihc::dwidth<512>, ihc::awidth<4>, ihc::latency<0>, ihc::waitrequest<true>, ihc::aspace<3>> mm_host_t3; I thought to ask in case you could clarify how to check what this assertion refers to. Let me know if you would require more details. Regards, Noah1.9KViews0likes7CommentsRe: vlog-7 "Failed to open design unit file in read mode" error during simulation for Agilex7 board
Hello once more @BoonBengT_Altera! I don't have a design to share, but I have interesting news nonetheless. I have tried making multiple changes to the design (and, in particular, to the confidential part of it), and all the changes I have tried seemed to resolve the error, so I cannot share a design replicating it. For example, changing the name of the component from "channel_compensation" to "c_comp" solves the error. I tried some other smaller changes, but most surprisingly, reverting to the original code after that did not throw the error. This was for the second design that I mentioned. The original design which threw a similar error also worked after shortening both the component name and changing the directory to one with a shorter path. My guess is that it did in fact have something to do with maximum path length. This does not really explain why one of the designs failed, then worked again after changing it and undoing the changes... But in any case, I no longer have a problem when trying to simulate my designs. My advice for anyone facing a similar problem: try shortening the path and the component name. Thank you and excuse me for not being able to provide clearer information! Regards, Noah2.5KViews0likes0CommentsRe: vlog-7 "Failed to open design unit file in read mode" error during simulation for Agilex7 board
Hello @BoonBengT_Altera Thank you for the recommendations, I will work on that to hopefully provide a design which I can share to see if the error can be replicated. Meanwhile, while trying to simulate a parallel project, I received a similar error: # ** Error: (vlog-7) Failed to open design unit file "../../../components/channel_compensation/channel_compensation/channel_compensation_internal_10/sim/channel_compensation_i_iowr_bl_eststream0000hannel_compensation0.sv" in read mode. # No such file or directory. (errno = ENOENT) This time it is apparent that the unit involved has something to do with a Stream Interface (estStream) for my channel_compensation component, but again, this file does seem to exist in the specified folder. Perhaps this indicates that the previous error was not an isolated problem. In any case, I hope to be back soon with a design to share. Thank you and regards, Noah2.6KViews0likes0CommentsRe: vlog-7 "Failed to open design unit file in read mode" error during simulation for Agilex7 board
Hello @BoonBengT_Altera! Please excuse my delay. I have been able to simulate other HLS projects for the same target device, so perhaps the issue lies with this specific component. I cannot share the project for reasons of confidentiality, but it deals with matrix inversion. I was thinking about whether it would be possible to create a different example project that also uses this component which results in error, but I am not sure how to do that! About the incorrect path, it seems like it appears correctly on the log. I checked the absolute path length in case it was too long. The total character count from the disk to the file, both included, is 248 characters. That is close to the maximum path length, but not quite, if I am not mistaken. I will let you know if I find something like that. Meanwhile, I share this clarification that I have been able to successfully simulate other projects. Regards, Noah2.8KViews0likes0Commentsvlog-7 "Failed to open design unit file in read mode" error during simulation for Agilex7 board
Good day, I am trying to simulate an HLS for an Agilex7 device. I'm using Quartus Prime Pro 24.2, and the corresponding versions of Questa - Intel FPGA Edition and HLS Compiler. Running on a Windows 11 Pro 23H2 computer. After launching compilation, simulation, etc. on the command window, the following message results: HLS Elaborate verification testbench FAILED. See (...)/luinv.prj/debug.log for details. Error: Cosim testbench elaboration failed. When opening said debug.log, this is the only error present: # Top level modules: # dpic_invmatrixursi # End time: 12:55:10 on Jan 23,2025, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024 # Start time: 12:55:10 on Jan 23,2025 # vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 -suppress 7061 ../../ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv -work avalon_concatenate_singlebit_conduits_10 # ** Error: (vlog-7) Failed to open design unit file "../../ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv" in read mode. # No such file or directory. (errno = ENOENT) # End time: 12:55:10 on Jan 23,2025, Elapsed time: 0:00:00 # Errors: 1, Warnings: 0 # ** Error: c:/intelFPGA_pro/24.2/questa_fe/win64/vlog failed. # Executing ONERROR command at macro ./msim_compile.tcl line 7 # Errors: 1, Warnings: 0 I checked whether the file exists, and apparently it does. It is in the specified folder, and has full permissions as far as I can tell. The error appears when running msim_compile.tcl, which is located at (...)/luinv.prj/verification/tb/sim/ The file-path which causes the error is then: (...)/luinv.prj/verification/ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv Here is the path in which the file is present in my computer, followed by the path from the log: (...)/luinv.prj/verification/ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv (...)/luinv.prj/verification/ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_lrbideq.sv I include it here in case I may be unwittingly blind, but I see no difference between these paths. Any ideas on what may cause this error? Thank you and regards, Noah3KViews0likes7CommentsRe: Error when running Power Analyzer with .vcd file in Quartus Prime Pro 24.2
Hello again, I tried two ways of generating it: 1) During the msim_run.tcl simulation script, by using the following code: [...] vcd file and_testbench.vcd vcd add -r /* run -all vcd flush [...] 2) Generating a .wlf file as is done by default in the msim_run.tcl generated by HLS Compiler, and then using the wlf2vcd tool in the Questasim command window. The .wlf file is set to be generated in the part of the code immediately preceding the code shown above: [...] set StdArithNoWarnings 1 set USER_DEFINED_ELAB_OPTIONS "+nowarnTFMPC -dpioutoftheblue 1 -sv_lib $fname_svlib -nodpiexports -wlf ../../vsim.wlf - voptargs=+acc" elab onfinish {stop} quietly set StdArithNoWarnings 1 log -r * [...] Regards, Noah4.6KViews0likes0Comments