uniqueMR
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Re: Partial Reconfiguration in oneAPI
Hi whitepau, Thanks for following up with this issue. I noticed the digram and the clarification that "the oneAPI ASP is in the PR region of the AFU and relies on the compiled database of the static region(FIM) to interface with the host and the board peripherals". However, this seems to be different from my observation on the generated project files. If I run 'make fpga' following oneAPI-samples, there will be a quartus project generated in vector_add.fpga.prj and named as quartus_compile.qpf. I checked this project in Quartus and found there is no logic lock region and only a single partition for the kernel, which is of 'Default' type instead of 'Reconfigurable'. In the chip planner, the kernel also seems to be placed and routed without any constraints. Moreover, even if the kernel is mapped into PR by default, does oneAPI support customized floorplan for PR region, such as: * change the place and size of the PR region? * assign two separate logic lock regions for two kernels, instead of putting them in the same PR region? * reconfigure a kernel (load other partitions as database files, and re-bind the target partition to a new entity)? I really appreciate your ideas on these issues. Thanks a lot. Best regards, RunlongPartial Reconfiguration in oneAPI
I'm working on a PR related project, and I plan to raise the abstraction level to HLD using oneAPI. I'm thinking of what is the typical workflow to utilize PR in a oneAPI design. # example application Using the following oneAPI-samples as an example, main() is the host code and will be compiled into assembly instructions; VectorAdd is the kernel function and will be synthesized into RTL, and placed and routed on the FPGA fabric. If that is the case, can I make VectorAdd a reconfigurable partition, and assign a logic lock region to constraint the PnR of VectorAdd? # typical PR flow I already have the experience of PR in Quartus Prime Pro. The floorplan for PR is usually done in post-synthesis stage, where a PR module defined in RTL is configured as 'reconfigurable' in Design Partition Window and constrained in Logic Lock Regions Window. # oneAPI flow I've just gone through oneAPI fpga compile example. If I run 'make fpga', I'll get an executable file with well-crafted bitstream, which means synthesis, PnR and assembly are all accomplished, without an intermediate step (like the post-synthesis step in typical PR flow) to floorplan for PR. If PR is supported by oneAPI, what is expected to be the intermediate step for design partition and logic lock region? I would appreciate it if someone can provide any ideas on this issue. Best, RunlongRe: 'make fpga_sim' Errors in Getting Started with oneAPI
Hi whitepau, I've generated the license for questa starter edition and configured the environmental variable in my ~/.bashrc, but it still reports the same issue: Below is how I configure the license file in ~/.bashrc: and also the content of my license file to make sure I get the proper one: I attach my current sim report to this thread. Are there any clues on further resolving this issue? Thanks a lot. Best regards, RunlongRe: 'make fpga_sim' Errors in Getting Started with oneAPI
Hi whitepau, I checked the vector_add_fpga_sim.log file, and it reports some license issue. I've already configured the LM_LICENSE_FILE variable but without the other two (SALT_LICENSE_SERVER and MGLS_LICENSE_FILE). With my LM_LICENSE_FILE, I have full access to Quartus Prime Pro 24.1 with Agilex 7 device support. What should I do with the other two to support oneAPI workflow? I also checked my Quartus device files and found that both Agilex 7 device support and Agilex common files had been installed. Do you have any other clues on resolving this issue? Thanks a lot. Best regards, Runlong'make fpga_sim' Errors in Getting Started with oneAPI
Hi, I'm getting started with oneAPI following oneAPI samples for FPGAs, and run into errors when 'make fpga_sim': The referred lines of the makefile are: These are the steps I followed: * git clone https://github.com/oneapi-src/oneAPI-samples.git * cd ./oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile * mkdir build * cd build * cmake .. -DFPGA_DEVICE=Agilex7 -DPART=2 * make fpga_emu (succeed) * make report (succeed) * make fpga_sim (failed) Does anyone have a clue? Thanks Best, RunlongRe: Typical way of loading runtime to Arm core (HPS)
Hi Jeet, Thank you for following up. Kevin said he would help me getting BSP/ASP for my agilex7 i-series devkit. Now I'm still waiting for his feedback. Could you still keep this thread if there's no other way for me to catch up with any updates? Thanks a lot. Best, RunlongRe: Typical way of loading runtime to Arm core (HPS)
Hi Kevin, Thank you so much for your time and effort. Yes, using ARM host is NOT a strong requirements for me at this point. I mentioned the ARM core just because I related it to my other project experience in the past. In the end, I will follow what oneAPI workflow expects me to do. I really appreciate that you can help me with BSP/ASP for I-series Devkit. Thanks, RunlongRe: Typical way of loading runtime to Arm core (HPS)
Hi Kevin Xu, By mentioning "You can usually get the ASP from your board vendor, or it can be generated by following this guide", does it mean I can skip generating BSP/ASP myself if I am able to get those support packages from, as you suggested, the board vendor? Now the guidance on ofs.github.io seems pretty scary to me. I spent two days without figuring out where should I start with. Each step seems to have a bunch of prerequisits and assumptions. I think those steps might be too much before I can run a simple line of 'helloWorld' and become the first-day learner of oneAPI. If I can somehow get the well-crafted BSP/ASP, does it mean I can start with something like 'aocl install <BSP_root_folder>'? That will make my life much easier. Thanks! Best, Runlong
