New Contributor
ContributorHi Runlong,
oneAPI FPGA Acceleration does Partial Reconfiguration for you, depending on the BSP.
BSPs crafted using OFS will have a structure like in this graphic (from the OFS documentation). As you can see, there is a PR region that contains your kernel code. The BSP is 'logic-locked' and your Application Kernel is counted as the 'PR region'.
I'm not sure if it's still the case, but there used to be an option for a 'flat compile' that would also recompile the 'logic-locked' region as well. this could sometimes help in cases where the kernel was large.
I will ask a domain expert to weigh in.
New ContributorHi whitepau,
Thanks for following up with this issue. I noticed the digram and the clarification that "the oneAPI ASP is in the PR region of the AFU and relies on the compiled database of the static region(FIM) to interface with the host and the board peripherals". However, this seems to be different from my observation on the generated project files.
If I run 'make fpga' following oneAPI-samples, there will be a quartus project generated in vector_add.fpga.prj and named as quartus_compile.qpf. I checked this project in Quartus and found there is no logic lock region and only a single partition for the kernel, which is of 'Default' type instead of 'Reconfigurable'.
In the chip planner, the kernel also seems to be placed and routed without any constraints.
Moreover, even if the kernel is mapped into PR by default, does oneAPI support customized floorplan for PR region, such as:
* change the place and size of the PR region?
* assign two separate logic lock regions for two kernels, instead of putting them in the same PR region?
* reconfigure a kernel (load other partitions as database files, and re-bind the target partition to a new entity)?
I really appreciate your ideas on these issues. Thanks a lot.
Best regards,
Runlong
ContributorThis depends on the value you set for the -Xstarget compiler flag.
If you choose to target a device family or OPN, e.g. -Xstarget=Agilex7, you will get an IP with a simple wrapper project with vitrtual pins that you can use to accurately gauge fmax and area utilization.
If you choose a BSP and board variant, you will get the PR system. You can poll your system for available BSPs using the aoc -list-boards command. The board list that is printed out will be of the form
$> aoc -list-boards
Board list:
<board-variant>
Board Package: <path/to/board/package>/board-support-package
<board-variant2>
Board Package: <path/to/board/package>/board-support-package
None of the enhancements you mentioned are supported
