PVeli
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Regarding writing test bench for Intel OpenCL generated code.
I donot have Mentor graphics Model SIm software with me. However I have Aldec Riviera pro tool. Can you please help how to identify the DUT and procedure for writing test bench. Intel has given simulator support only to Mentor Graphics Model sim., using -march=simulator option where the host code is being drivern as Test bench.How to do that for other tools ?924Views0likes1CommentRe: OpenCL RTL simulation using ModelSim-Intel FPGA Edition or Aldec Riviera Pro
I have only Intel FPGA -Modelsim version which is not compatible with OpenCL RTL simulation. They have mentioned only running simulation with Mentor Graphics Version Only, I dont know where they are getting test bench to do simulation. Atleast if you can help me to point the test bench template, which are used, it can help to me do simulation with Third Party tool like Riviera Pro.2.1KViews0likes0CommentsOpenCL RTL simulation using ModelSim-Intel FPGA Edition or Aldec Riviera Pro
I have ModelSim-Intel FPGA edition and Aldec Riviera Pro simulator in my system.I donot have MentorGraphics ModelSim with me. When I am simulating the vector_add OpenCL example design using the following procedure. $aoc -march=simulator device/vector_add.cl -o bin/vector_add.aocx -board=a10gx $make $CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 bin/host I have got the following error. Platform: Intel(R) FPGA SDK for OpenCL(TM) Using 1 device(s) SimulatorDevice : Multi-process Simulator (aclmsim0) Using AOCX: vector_add.aocx The simulation process encountered an error and has aborted. Error: The simulator's process ended unexpectedly. Check /raid/dpfd/projects/Compression/simulation_demo/vector_add/bin/transcript.log for details. host: src/hls_cosim_ipc_socket.cpp:212: void IPCSocketMaster::connect(): Assertion `sockfd != -1 && "IPCSocketMaster::connect() call to accept() failed"' failed. It was given in the book, probably the ModelSim-IntelFPGA edition is not compatible with OpenCL RTL simulation, however I have another full-fledged simulator Aldec-Riviera Pro.I can compile and simulate all Intel Arria10 IPs in that. I am sure there must be a way for OpenCL-RTL simulation in Riviera PRO as well. There must be a macro such as CL_CONTEXT_MPSIM_DEVICE_INTELFPGA, for Riviera Pro or any other tools as well. Please help me with the procedure required to do that !2.2KViews0likes4Comments-legacy-emulator for Intel FPGA SDK 19.3 Pro
I am receiving the following error when running -legacy-emulator Platform: Intel(R) FPGA Emulation Platform for OpenCL(TM) Using AOCX: traffic_stn.aocx Context callback: clCreateProgramWithBinary failed ERROR: CL_INVALID_BINARY Location: ../common/src/AOCLUtils/opencl.cpp:392 Failed to create program with binary1.1KViews0likes1CommentRe: Error in using emulator mode with SDK 20.1 for hello_world example
Hello Anil, When I am using legacy emulator for 19.3 I am getting following error. Please suggest me asap. Platform: Intel(R) FPGA Emulation Platform for OpenCL(TM) Using AOCX: traffic_stn.aocx Context callback: clCreateProgramWithBinary failed ERROR: CL_INVALID_BINARY Location: ../common/src/AOCLUtils/opencl.cpp:392 Failed to create program with binary3.1KViews0likes1CommentRe: Emulator v19.3 is much slower than v19.1/18.1
Using AOCX: traffic_stn.aocx Context callback: clCreateProgramWithBinary failed ERROR: CL_INVALID_BINARY Location: ../common/src/AOCLUtils/opencl.cpp:392 Failed to create program with binary I am getting this error with -legacy emulator , please help me2.9KViews0likes0Comments