OpenCL RTL simulation using ModelSim-Intel FPGA Edition or Aldec Riviera Pro
I have ModelSim-Intel FPGA edition and Aldec Riviera Pro simulator in my system.I donot have MentorGraphics ModelSim with me. When I am simulating the vector_add OpenCL example design using the following procedure.
$aoc -march=simulator device/vector_add.cl -o bin/vector_add.aocx -board=a10gx
$make
$CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 bin/host
I have got the following error.
Platform: Intel(R) FPGA SDK for OpenCL(TM)
Using 1 device(s)
SimulatorDevice : Multi-process Simulator (aclmsim0)
Using AOCX: vector_add.aocx
The simulation process encountered an error and has aborted.
Error: The simulator's process ended unexpectedly. Check /raid/dpfd/projects/Compression/simulation_demo/vector_add/bin/transcript.log for details.
host: src/hls_cosim_ipc_socket.cpp:212: void IPCSocketMaster::connect(): Assertion `sockfd != -1 && "IPCSocketMaster::connect() call to accept() failed"' failed.
It was given in the book, probably the ModelSim-IntelFPGA edition is not compatible with OpenCL RTL simulation, however I have another full-fledged simulator Aldec-Riviera Pro.I can compile and simulate all Intel Arria10 IPs in that. I am sure there must be a way for OpenCL-RTL simulation in Riviera PRO as well.
There must be a macro such as CL_CONTEXT_MPSIM_DEVICE_INTELFPGA, for Riviera Pro or any other tools as well. Please help me with the procedure required to do that !