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Inquiry about Development Kit Options and Device Model Compatibility for CXL Design Examples
When generating a CXL design example, the Development Kit options in the configuration menu only include DK-DEV-AGI027R1BES and DK-DEV-AGI027RBES, with DK-DEV-AGI027-RA not available. If I want to generate a design example corresponding to RA, should I select DK-DEV-AGI027RBES? I heard that DK-DEV-AGI027RBES is a test version, while DK-DEV-AGI027-RA is the production version. Additionally, if RBES is chosen, can the device model AGIB027R29A1E1VB corresponding to RA still be used? OS: Windows11 Quartus version:24.2Inquiry about Device Compatibility and Version Support for AGIB027R29A1E2VR3 in Quartus Prime Pro V
During the New Project stage, the device model AGIB027R29A1E2VR3 is not available, but the Development Kit DK-DEV-AGI027R1BES is present. However, in the device model list, AGIB027R29A1E2VRC is found. Are VRC and VR3 the same device? Or is it that version 24.2 does not support the device AGIB027R29A1E2VR3? OS: Windows11 Quartus version:24.2Error: Quartus Prime Assembler was unsuccessful？CXL design example.
OS: Windows11 Quartus version:24.2 Device：AGIB027R29A1E1VB Development Kit: Agilex 7 FPGA I-Series Development Kit 2xR-Tile and 1xF-Tile DK-DEV-AGI027-RA Unable to generate CXL design example with Tile 14C or 15C： Error persists after checking and replacing the license. Error persists after changing the device type to AGIB027R29A1E2VR3 and Development Kit to R1BES. How should I solve this problem? Is it related to the Quartus Prime Pro software version?CXL design example simulation:
Hello! When I use Avery VIP and CXL testbench to simulate cxl design exmaple, the following error occurs. # > sh vcs_sim_dtl_save.sh <cxl design example directory> OS: centos7.4 Quartus Prime Pro version:23.4 vcs version: 2022.06 verdi version:2022.06 Since centos7 only supports quartus prime pro to version 22.2, the 23.2 and 23.4 versions we installed on the current machine cannot be opened, but the installation process can proceed normally. I have asked other engineers about their experience in successfully installing quartus 23.2 and below on centos7, but I cannot refer to it at the moment. Please tell me how should I solve this problem? Thank you!Intel R-Tile for CXL IP fails to generate Design Example
Hi, After configuring the Intel R-Tile for Compute Express Link IP in the Platform Designer, trying to generate the Example Design fails with: Info: intel_rtile_cxl_top_0: Generating Example Design ... Info: intel_rtile_cxl_top_0: Validating Parameters for Example Design Generation ... Info: intel_rtile_cxl_top_0: Parameters Valid for Example Design Generation ... Info: intel_rtile_cxl_top_0: Generating IP Core ... Error: add_fileset_file: No such file C:/Users/87146/AppData/Local/Temp/alt9481_6254809594632308622.dir/0002_intel_rtile_cxl_top_0_gen/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_170/synth/avmm_interconnect_network/ip/avmm_interconnect/cxl_compliance_slave/altera_avalon_mm_bridge_2001/synth/synth while executing "add_fileset_file "./$f_path" SYSTEM_VERILOG PATH $file" (procedure "::intel_rtile_cxl_top::ed::generate_ip_core" line 80) invoked from within "::intel_rtile_cxl_top::ed::generate_ip_core" (procedure "::intel_rtile_cxl_top::ed::create_ed" line 11) invoked from within "::intel_rtile_cxl_top::ed::create_ed " (procedure "callback_example_design" line 3) invoked from within "callback_example_design intel_rtile_cxl_top_0_ed" Error: Failed to generate example design ed to: D:\quartus_test\cxl_design_example\quartus_prj\intel_rtile_cxl_top_0_ed I have CXL IP License. I have already consulted the FAE I know and he said that there is no design example yet. And I want to know do you have this file: " R-Tile Intel FPGA IP for Compute Express Link* (CXL) Design Example User Guide." I see it in Intel® Agilex™ R-Tile Compute Express Link* 1.1/2.0 FPGA IP User Guide. Any suggestions? Thank you, Quinn.
