pudding_art
New Contributor
2 years agoIntel R-Tile for CXL IP fails to generate Design Example
Hi,
After configuring the Intel R-Tile for Compute Express Link IP in the Platform Designer, trying to generate the Example Design fails with:
Info: intel_rtile_cxl_top_0: Generating Example Design ... Info: intel_rtile_cxl_top_0: Validating Parameters for Example Design Generation ... Info: intel_rtile_cxl_top_0: Parameters Valid for Example Design Generation ... Info: intel_rtile_cxl_top_0: Generating IP Core ... Error: add_fileset_file: No such file C:/Users/87146/AppData/Local/Temp/alt9481_6254809594632308622.dir/0002_intel_rtile_cxl_top_0_gen/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_170/synth/avmm_interconnect_network/ip/avmm_interconnect/cxl_compliance_slave/altera_avalon_mm_bridge_2001/synth/synth while executing "add_fileset_file "./$f_path" SYSTEM_VERILOG PATH $file" (procedure "::intel_rtile_cxl_top::ed::generate_ip_core" line 80) invoked from within "::intel_rtile_cxl_top::ed::generate_ip_core" (procedure "::intel_rtile_cxl_top::ed::create_ed" line 11) invoked from within "::intel_rtile_cxl_top::ed::create_ed " (procedure "callback_example_design" line 3) invoked from within "callback_example_design intel_rtile_cxl_top_0_ed" Error: Failed to generate example design ed to: D:\quartus_test\cxl_design_example\quartus_prj\intel_rtile_cxl_top_0_ed
I have CXL IP License. I have already consulted the FAE I know and he said that there is no design example yet.
And I want to know do you have this file: " R-Tile Intel FPGA IP for Compute Express Link* (CXL) Design Example User Guide." I see it in Intel® Agilex™ R-Tile Compute Express Link* 1.1/2.0 FPGA IP User Guide.
Any suggestions?
Thank you,
Quinn.