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pudding_art's avatar
pudding_art
Icon for New Contributor rankNew Contributor
2 years ago

Intel R-Tile for CXL IP fails to generate Design Example

Hi, After configuring the Intel R-Tile for Compute Express Link IP in the Platform Designer, trying to generate the Example Design fails with: Info: intel_rtile_cxl_top_0: Generating Example De...
JonWay_C_Intel's avatar
JonWay_C_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi there,

The R-Tile Intel FPGA IP for Compute Express Link* (CXL) Design Example User Guide is not publicly available now.

You can request for the document via your local FAE.

The document number: 763328

Link to doc: https://cdrdv2.intel.com/v1/dl/getContent/779294?explicitVersion=true

FAE should be able to assess your need and provide the document. You can provide the above doc# and link. FAE can access the link and provide to you.